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PMCCFILTR_EL0

Performance Monitors Cycle Count Filter Register

Determines the modes in which the Cycle Counter, PMCCNTR_EL0, increments.

Configuration

AArch64 System register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCCFILTR[31:0].

AArch64 System register PMCCFILTR_EL0 bits [63:32] are architecturally mapped to External register PMCCFILTR_EL0[63:32] when FEAT_PMUv3_TH is implemented, or FEAT_PMUv3p8 is implemented, or FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3_SME is implemented.

AArch64 System register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to External register PMCCFILTR_EL0[31:0].

This register is present only when FEAT_PMUv3 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to PMCCFILTR_EL0 are UNDEFINED.

Attributes

PMCCFILTR_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0VSRES0
PUNSKNSUNSHMRES0SHRES0RLKRLURLHRES0

Bits [63:58]:

Reserved, RES0.

VS, bits [57:56] when FEAT_PMUv3_SME is implemented:

SVE mode filtering. Controls counting cycles in Streaming and Non-streaming SVE modes.

VSMeaning
0b00

This mechanism has no effect on the filtering of cycles.

0b01

The PE does not count cycles in Streaming SVE mode.

0b10

The PE does not count cycles in Non-streaming SVE mode.

All other values are reserved.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [55:32]:

Reserved, RES0.

P, bit [31]:

EL1 filtering. Controls counting cycles in EL1.

PMeaning
0b0

This mechanism has no effect on filtering of cycles.

0b1

The PE does not count cycles in EL1.

If Secure and Non-secure states are implemented, then counting cycles in Non-secure EL1 is further controlled by PMCCFILTR_EL0.NSK.

If FEAT_RME is implemented, then counting cycles in Realm EL1 is further controlled by PMCCFILTR_EL0.RLK.

If EL3 is implemented, then counting cycles at EL3 is further controlled by PMCCFILTR_EL0.M.

The reset behavior of this field is:

U, bit [30]:

EL0 filtering. Controls counting cycles in EL0.

UMeaning
0b0

This mechanism has no effect on filtering of cycles.

0b1

The PE does not count cycles in EL0.

If Secure and Non-secure states are implemented, then counting cycles in Non-secure EL0 is further controlled by PMCCFILTR_EL0.NSU.

If FEAT_RME is implemented, then counting cycles in Realm EL0 is further controlled by PMCCFILTR_EL0.RLU.

The reset behavior of this field is:

NSK, bit [29] when EL3 is implemented:

Non-secure EL1 filtering. Controls counting cycles in Non-secure EL1. If PMCCFILTR_EL0.NSK is not equal to PMCCFILTR_EL0.P, then the PE does not count cycles in Non-secure EL1. Otherwise, this mechanism has no effect on filtering of cycles in Non-secure EL1.

NSKMeaning
0b0

When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.P == 1, the PE does not count cycles in Non-secure EL1.

0b1

When PMCCFILTR_EL0.P == 0, the PE does not count cycles in Non-secure EL1.

When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

NSU, bit [28] when EL3 is implemented:

Non-secure EL0 filtering. Controls counting cycles in Non-secure EL0. If PMCCFILTR_EL0.NSU is not equal to PMCCFILTR_EL0.U, then the PE does not count cycles in Non-secure EL0. Otherwise, this mechanism has no effect on filtering of cycles in Non-secure EL0.

NSUMeaning
0b0

When PMCCFILTR_EL0.U == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.U == 1, the PE does not count cycles in Non-secure EL0.

0b1

When PMCCFILTR_EL0.U == 0, the PE does not count cycles in Non-secure EL0.

When PMCCFILTR_EL0.U == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

NSH, bit [27] when EL2 is implemented:

EL2 filtering. Controls counting cycles in EL2.

NSHMeaning
0b0

The PE does not count cycles in EL2.

0b1

This mechanism has no effect on filtering of cycles.

If EL3 is implemented and FEAT_SEL2 is implemented, then counting cycles in Secure EL2 is further controlled by PMCCFILTR_EL0.SH.

If FEAT_RME is implemented, then counting cycles in Realm EL2 is further controlled by PMCCFILTR_EL0.RLH.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

M, bit [26] when EL3 is implemented:

EL3 filtering. Controls counting cycles in EL3. If PMCCFILTR_EL0.M is not equal to PMCCFILTR_EL0.P, then the PE does not count cycles in EL3. Otherwise, this mechanism has no effect on filtering of cycles in EL3.

MMeaning
0b0

When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.P == 1, the PE does not count cycles in EL3.

0b1

When PMCCFILTR_EL0.P == 0, the PE does not count cycles in EL3.

When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bit [25]:

Reserved, RES0.

SH, bit [24] when EL3 is implemented and FEAT_SEL2 is implemented:

Secure EL2 filtering. Controls counting cycles in Secure EL2. If PMCCFILTR_EL0.SH is equal to PMCCFILTR_EL0.NSH, then the PE does not count cycles in Secure EL2. Otherwise, this mechanism has no effect on filtering of cycles in Secure EL2.

SHMeaning
0b0

When PMCCFILTR_EL0.NSH == 0, the PE does not count cycles in Secure EL2.

When PMCCFILTR_EL0.NSH == 1, this mechanism has no effect on filtering of cycles.

0b1

When PMCCFILTR_EL0.NSH == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.NSH == 1, the PE does not count cycles in Secure EL2.

The reset behavior of this field is:

When Secure EL2 is not implemented, access to this field is RES0 .

Otherwise:

Reserved, RES0.

Bit [23]:

Reserved, RES0.

RLK, bit [22] when FEAT_RME is implemented:

Realm EL1 filtering. Controls counting cycles in Realm EL1. If PMCCFILTR_EL0.RLK is not equal to PMCCFILTR_EL0.P, then the PE does not count cycles in Realm EL1. Otherwise, this mechanism has no effect on filtering of cycles in Realm EL1.

RLKMeaning
0b0

When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.P == 1, the PE does not count cycles in Realm EL1.

0b1

When PMCCFILTR_EL0.P == 0, the PE does not count cycles in Realm EL1.

When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

RLU, bit [21] when FEAT_RME is implemented:

Realm EL0 filtering. Controls counting cycles in Realm EL0. If PMCCFILTR_EL0.RLU is not equal to PMCCFILTR_EL0.U, then the PE does not count cycles in Realm EL0. Otherwise, this mechanism has no effect on filtering of cycles in Realm EL0.

RLUMeaning
0b0

When PMCCFILTR_EL0.U == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.U == 1, the PE does not count cycles in Realm EL0.

0b1

When PMCCFILTR_EL0.U == 0, the PE does not count cycles in Realm EL0.

When PMCCFILTR_EL0.U == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

RLH, bit [20] when FEAT_RME is implemented:

Realm EL2 filtering. Controls counting cycles in Realm EL2. If PMCCFILTR_EL0.RLH is equal to PMCCFILTR_EL0.NSH, then the PE does not count cycles in Realm EL2. Otherwise, this mechanism has no effect on filtering of cycles in Realm EL2.

RLHMeaning
0b0

When PMCCFILTR_EL0.NSH == 0, the PE does not count cycles in Realm EL2.

When PMCCFILTR_EL0.NSH == 1, this mechanism has no effect on filtering of cycles.

0b1

When PMCCFILTR_EL0.NSH == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.NSH == 1, the PE does not count cycles in Realm EL2.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [19:0]:

Reserved, RES0.

Access Instructions

PMCCFILTR_EL0 can also be accessed by using PMXEVTYPER_EL0 with PMSELR_EL0.SEL set to 0b11111.

Permitted reads and writes of PMCCFILTR_EL0 are RAZ/WI if all of the following are true:

Permitted writes of PMCCFILTR_EL0 are ignored if all of the following are true:

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMCCFILTR_EL0

(op0 = 0b11, op1 = 0b011, CRn = 0b1110, CRm = 0b1111, op2 = 0b111)

if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PSTATE.EL == EL0 then if PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMCCFILTR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().UEN == '1' && PMUACR_EL1().C == '0' then X{64}(t) = Zeros{64}; else X{64}(t) = PMCCFILTR_EL0(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMCCFILTR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCCFILTR_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMCCFILTR_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMCCFILTR_EL0(); end;

MSR PMCCFILTR_EL0, <Xt>

(op0 = 0b11, op1 = 0b011, CRn = 0b1110, CRm = 0b1111, op2 = 0b111)

if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PSTATE.EL == EL0 then if PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMCCFILTR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().UEN == '1' && (PMUACR_EL1().C == '0' || PMUSERENR_EL0().CR == '1') then return; else PMCCFILTR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMCCFILTR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMCCFILTR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMCCFILTR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMCCFILTR_EL0() = X{64}(t); end;

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