PMBLIMITR_EL1

This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMBLIMITR_EL1 are UNDEFINED.

Attributes

Field descriptions

LIMIT, bits [63:12]:

Bits [11:8]:

nVM, bit [7] when FEAT_SPE_nVM is implemented:

Address mode.

nVM	Meaning
0b0	The Profiling Buffer pointers are virtual addresses.
0b1	The Profiling Buffer pointers are: Physical address in the owning security state if the owning translation regime has no stage 2 translation. Intermediate physical addresses in the owning security state if the owning translation regime has stage 2 translations.

nVM

Meaning

0b0

The Profiling Buffer pointers are virtual addresses.

0b1

The Profiling Buffer pointers are:

Physical address in the owning security state if the owning translation regime has no stage 2 translation.
Intermediate physical addresses in the owning security state if the owning translation regime has stage 2 translations.

If the Effective value of PMSCR_EL2.EnVM is 0, then the PE ignores the value of this field, and the Profiling Buffer pointers are always virtual addresses.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Access to this field is RW.

Otherwise:

Bit [6]:

PMFZ, bit [5] when FEAT_SPEv1p2 is implemented:

Freeze PMU on SPE event. Stop PMU event counters when PMBSR_EL1.S == 1.

PMFZ	Meaning
0b0	Do not freeze PMU event counters on Statistical Profiling Buffer Management event.
0b1	Freeze PMU event counters on Statistical Profiling Buffer Management event.

The PMU event counters affected by this control is controlled by PMCR_EL0.FZS and, if EL2 is implemented, MDCR_EL2.HPMFZS. See the descriptions of these control bits for more information.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [4:3]:

FM, bits [2:1]:

Fill mode.

FM	Meaning	Applies when
0b00	Fill mode. Stop collection and raise maintenance interrupt on buffer fill.
0b10	Discard mode. All output is discarded.	When FEAT_SPEv1p2 is implemented

All other values are reserved.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

E, bit [0]:

E	Meaning
0b0	All output is discarded.
0b1	Profiling buffer enabled.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMBLIMITR_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b1001, CRm = 0b1010, op2 = 0b000)

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMBLIMITR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2PB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x800); else X{64}(t) = PMBLIMITR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMBLIMITR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMBLIMITR_EL1(); end;

MSR PMBLIMITR_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b1001, CRm = 0b1010, op2 = 0b000)

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMBLIMITR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2PB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x800) = X{64}(t); else PMBLIMITR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMBLIMITR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMBLIMITR_EL1() = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LIMIT
LIMIT																				RES0				nVM	RES0	PMFZ	RES0		FM		E

Configuration

Attributes

Field descriptions

LIMIT, bits [63:12]:

Bits [11:8]:

nVM, bit [7] when FEAT_SPE_nVM is implemented:

Otherwise:

Bit [6]:

PMFZ, bit [5] when FEAT_SPEv1p2 is implemented:

Otherwise:

Bits [4:3]:

FM, bits [2:1]:

E, bit [0]:

Access Instructions