PAN

This register is present only when FEAT_PAN is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to PAN are UNDEFINED.

Attributes

Field descriptions

Bits [63:23]:

PAN, bit [22]:

Privileged Access Never.

PAN	Meaning
0b0	Privileged reads and write are not disabled by this mechanism.
0b1	Disables privileged read and write accesses to addresses accessible at EL0 for an enabled stage 1 translation regime that defines the EL0 permissions.

The value of this bit is usually preserved on taking an exception, except in the following situations:

When the target of the exception is EL1, and the value of the SCTLR_EL1.SPAN bit is 0, this bit is set to 1.
When the target of the exception is EL2, the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, and the value of the SCTLR_EL2.SPAN bit is 0, this bit is set to 1.
When the target of the exception is EL2, the Effective value of HCR_EL2.{E2H, TGE} is {1, 0}, and the value of the SCTLR_EL2.SPAN bit is 0, the following applies:
- If FEAT_NV3 is not implemented, it is IMPLEMENTATION SPECIFIC whether this bit is set to 1. Arm recommends that it is set to 1 in this case.
- If FEAT_NV3 is implemented, this bit is set to 1.

Bits [21:0]:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PAN

(op0 = 0b11, op1 = 0b000, CRn = 0b0100, CRm = 0b0010, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_PAN) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then X{64}(t) = Zeros{41} :: PSTATE.PAN :: Zeros{22}; elsif PSTATE.EL == EL2 then X{64}(t) = Zeros{41} :: PSTATE.PAN :: Zeros{22}; elsif PSTATE.EL == EL3 then X{64}(t) = Zeros{41} :: PSTATE.PAN :: Zeros{22}; end;

MSR PAN, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0100, CRm = 0b0010, op2 = 0b011)

if !(IsFeatureImplemented(FEAT_PAN) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then PSTATE.PAN = X{64}(t)[22]; elsif PSTATE.EL == EL2 then PSTATE.PAN = X{64}(t)[22]; elsif PSTATE.EL == EL3 then PSTATE.PAN = X{64}(t)[22]; end;

MSR PAN, #<imm>

(op0 = 0b00, op1 = 0b000, CRn = 0b0100, op2 = 0b100)