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NVHCR_EL2

Nested Virtual Hypervisor Configuration Register

Provides storage for a virtual view of HCR_EL2 under nested virtualization. Except for the TGE bit, all bits in this register are simply stateful and have no effect on PE behavior.

Configuration

This register is present only when FEAT_NV3 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to NVHCR_EL2 are UNDEFINED.

Attributes

NVHCR_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0TWEDELTWEDEnTID5DCTATATTLBOSTTLBISEnSCXTTOCUAMVOFFENTICABTID4GPFFIENFWBNV2ATNV1NVAPIAPKRES0TEATERRTLORE2HIDCD
RWTRVMHCDTDZTGETVMTTLBTPUTPCPTSWTACRTIDCPTSCTID3TID2TID1TID0TWETWIDCRES0BSUFBVSEVIVFAMOIMOFMOPTWSWIOVM

Bits [63:61]:

Reserved, RES0.

TWEDEL, bit [60] when FEAT_TWED is implemented:

Storage for the virtual view of HCR_EL2.TWEDEL under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TWEDEn, bit [59] when FEAT_TWED is implemented:

Storage for the virtual view of HCR_EL2.TWEDEn under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TID5, bit [58] when FEAT_MTE2 is implemented:

Storage for the virtual view of HCR_EL2.TID5 under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

DCT, bit [57] when FEAT_MTE2 is implemented:

Storage for the virtual view of HCR_EL2.DCT under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

ATA, bit [56] when FEAT_MTE2 is implemented:

Storage for the virtual view of HCR_EL2.ATA under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TTLBOS, bit [55] when FEAT_EVT is implemented:

Storage for the virtual view of HCR_EL2.TTLBOS under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TTLBIS, bit [54] when FEAT_EVT is implemented:

Storage for the virtual view of HCR_EL2.TTLBIS under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

EnSCXT, bit [53] when FEAT_CSV2_2 is implemented:

Storage for the virtual view of HCR_EL2.EnSCXT under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TOCU, bit [52] when FEAT_EVT is implemented:

Storage for the virtual view of HCR_EL2.TOCU under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

AMVOFFEN, bit [51] when FEAT_AMUv1p1 is implemented:

Storage for the virtual view of HCR_EL2.AMVOFFEN under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TICAB, bit [50] when FEAT_EVT is implemented:

Storage for the virtual view of HCR_EL2.TICAB under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TID4, bit [49] when FEAT_EVT is implemented:

Storage for the virtual view of HCR_EL2.TID4 under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

GPF, bit [48] when FEAT_RME is implemented:

Storage for the virtual view of HCR_EL2.GPF under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

FIEN, bit [47] when FEAT_RASv1p1 is implemented:

Storage for the virtual view of HCR_EL2.FIEN under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

FWB, bit [46] when FEAT_S2FWB is implemented:

Storage for the virtual view of HCR_EL2.FWB under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

NV2, bit [45] when FEAT_NV2 is implemented:

Storage for the virtual view of HCR_EL2.NV2 under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

AT, bit [44] when FEAT_NV is implemented:

Storage for the virtual view of HCR_EL2.AT under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

NV1, bit [43] when FEAT_NV is implemented:

Storage for the virtual view of HCR_EL2.NV1 under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

NV, bit [42] when FEAT_NV is implemented:

Storage for the virtual view of HCR_EL2.NV under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

API, bit [41] when FEAT_PAuth is implemented:

Storage for the virtual view of HCR_EL2.API under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

APK, bit [40] when FEAT_PAuth is implemented:

Storage for the virtual view of HCR_EL2.APK under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

Bits [39:38]:

Reserved, RES0.

TEA, bit [37] when FEAT_RAS is implemented:

Storage for the virtual view of HCR_EL2.TEA under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TERR, bit [36] when FEAT_RAS is implemented:

Storage for the virtual view of HCR_EL2.TERR under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TLOR, bit [35] when FEAT_LOR is implemented:

Storage for the virtual view of HCR_EL2.TLOR under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

E2H, bit [34] when FEAT_VHE is implemented and FEAT_E2H0 is implemented:

Storage for the virtual view of HCR_EL2.E2H under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

when FEAT_VHE is implemented:

Storage for the virtual view of HCR_EL2.E2H under nested virtualization.

This field is RES1.

Otherwise:

Reserved, RES0.

ID, bit [33]:

Storage for the virtual view of HCR_EL2.ID under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

CD, bit [32]:

Storage for the virtual view of HCR_EL2.CD under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

RW, bit [31] when FEAT_AA32EL1 is implemented:

Storage for the virtual view of HCR_EL2.RW under nested virtualization.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TRVM, bit [30]:

Storage for the virtual view of HCR_EL2.TRVM under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

HCD, bit [29] when EL3 is not implemented:

Storage for the virtual view of HCR_EL2.HCD under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TDZ, bit [28]:

Storage for the virtual view of HCR_EL2.TDZ under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TGE, bit [27]:

Guest TGE control bit.

The reset behavior of this field is:

Accessing this field has the following behavior:

TVM, bit [26]:

Storage for the virtual view of HCR_EL2.TVM under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TTLB, bit [25]:

Storage for the virtual view of HCR_EL2.TTLB under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TPU, bit [24]:

Storage for the virtual view of HCR_EL2.TPU under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TPCP, bit [23]:

Storage for the virtual view of HCR_EL2.TPCP under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TSW, bit [22]:

Storage for the virtual view of HCR_EL2.TSW under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TACR, bit [21]:

Storage for the virtual view of HCR_EL2.TACR under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TIDCP, bit [20]:

Storage for the virtual view of HCR_EL2.TIDCP under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TSC, bit [19]:

Storage for the virtual view of HCR_EL2.TSC under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TID3, bit [18]:

Storage for the virtual view of HCR_EL2.TID3 under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TID2, bit [17]:

Storage for the virtual view of HCR_EL2.TID2 under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TID1, bit [16]:

Storage for the virtual view of HCR_EL2.TID1 under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TID0, bit [15] when FEAT_AA32 is implemented:

Storage for the virtual view of HCR_EL2.TID0 under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Otherwise:

Reserved, RES0.

TWE, bit [14]:

Storage for the virtual view of HCR_EL2.TWE under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

TWI, bit [13]:

Storage for the virtual view of HCR_EL2.TWI under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

DC, bit [12]:

Storage for the virtual view of HCR_EL2.DC under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Bit [11]:

Reserved, RES0.

BSU, bit [10]:

Storage for the virtual view of HCR_EL2.BSU under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

FB, bit [9]:

Storage for the virtual view of HCR_EL2.FB under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

VSE, bit [8]:

Storage for the virtual view of HCR_EL2.VSE under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

VI, bit [7]:

Storage for the virtual view of HCR_EL2.VI under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

VF, bit [6]:

Storage for the virtual view of HCR_EL2.VF under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

AMO, bit [5]:

Storage for the virtual view of HCR_EL2.AMO under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

IMO, bit [4]:

Storage for the virtual view of HCR_EL2.IMO under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

FMO, bit [3]:

Storage for the virtual view of HCR_EL2.FMO under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

PTW, bit [2]:

Storage for the virtual view of HCR_EL2.PTW under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

SWIO, bit [1]:

Storage for the virtual view of HCR_EL2.SWIO under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

VM, bit [0]:

Storage for the virtual view of HCR_EL2.VM under nested virtualization.

The reset behavior of this field is:

Accessing this field has the following behavior:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, NVHCR_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0101, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_NV3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR2_EL3().NV3En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_NV3) && EffectiveHCRX_EL2_NVTGE() == '1' then X{64}(t) = NVMem(0x078); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_SCR2) && SCR2_EL3().NV3En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = NVHCR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = NVHCR_EL2(); end;

MSR NVHCR_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0101, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_NV3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR2_EL3().NV3En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_NV3) && EffectiveHCRX_EL2_NVTGE() == '1' then NVMem(0x078) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_SCR2) && SCR2_EL3().NV3En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else NVHCR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then NVHCR_EL2() = X{64}(t); end;

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