MPAM Control Register (EL3)
Controls the generation of MPAM information for memory requests when executing at EL3 and at lower ELs.
AArch64 System register MPAMCTL_EL3 bit [63] is architecturally mapped to AArch64 System register MPAMCTL_EL2[63] when EL2 is implemented.
AArch64 System register MPAMCTL_EL3 bit [63] is architecturally mapped to AArch64 System register MPAMCTL_EL1[63].
This register is present only when FEAT_MPAMv2 is implemented. Otherwise, direct accesses to MPAMCTL_EL3 are UNDEFINED.
MPAMCTL_EL3 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPAMEN | nTRAPLOWER | RES0 | EN_ALT_IPMG | EN_ALT_IPARTID | RES0 | ||||||||||||||||||||||||||
| RES0 | |||||||||||||||||||||||||||||||
MPAM Enable. MPAM is enabled when MPAMEN == 1. When disabled, all PARTIDs and PMGs are output as their default value in the corresponding ID space.
| MPAMEN | Meaning |
|---|---|
| 0b0 |
The default PARTID and default PMG are output in MPAM information when executing at any ELn. |
| 0b1 |
MPAM information is output based on the MPAMn_ELx register for ELn according the MPAM configuration. |
The reset behavior of this field is:
Trap direct accesses to MPAM System registers that are not UNDEFINED from all ELn lower than EL3.
| nTRAPLOWER | Meaning |
|---|---|
| 0b0 |
Force direct accesses of MPAM System registers to trap to EL3. |
| 0b1 |
Do not force trapping of direct accesses of MPAM System registers to EL3. |
This trap is higher priority than any of the traps controlled by MPAM _EL2 registers.
The reset behavior of this field is:
Reserved, RES0.
Enables use of the alternative PMG configured in MPAM3_EL3.altPMG for instruction fetch accesses originating at EL3.
| EN_ALT_IPMG | Meaning |
|---|---|
| 0b0 |
The alternative PMG configured in MPAM3_EL3.altPMG is not used for generating MPAM information for instruction fetch accesses. |
| 0b1 |
The alternative PMG configured in MPAM3_EL3.altPMG is used for generating MPAM information for instruction fetch accesses. |
The reset behavior of this field is:
Reserved, RES0.
Enables use of the alternative PARTID configured in MPAM3_EL3.altPARTID for instruction fetch accesses originating at EL3.
| EN_ALT_IPARTID | Meaning |
|---|---|
| 0b0 |
The alternative PARTID configured in MPAM3_EL3.altPARTID is not used for generating MPAM information for instruction fetch accesses. |
| 0b1 |
The alternative PARTID configured in MPAM3_EL3.altPARTID is used for generating MPAM information for instruction fetch accesses. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, MPAMCTL_EL3
(op0 = 0b11, op1 = 0b110, CRn = 0b1010, CRm = 0b0101, op2 = 0b010)
if !IsFeatureImplemented(FEAT_MPAMv2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = MPAMCTL_EL3(); end;
MSR MPAMCTL_EL3, <Xt>
(op0 = 0b11, op1 = 0b110, CRn = 0b1010, CRm = 0b0101, op2 = 0b010)
if !IsFeatureImplemented(FEAT_MPAMv2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then MPAMCTL_EL3() = X{64}(t); end;
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