Monitor DCC Interrupt Enable Register
Enables interrupt requests to be signaled based on the DCC status flags.
AArch64 System register MDCCINT_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGDCCINT[31:0].
This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to MDCCINT_EL1 are UNDEFINED.
MDCCINT_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | RX | TX | RES0 | ||||||||||||||||||||||||||||
Reserved, RES0.
DCC interrupt request enable control for DTRRX. Enables a common COMMIRQ interrupt request to be signaled based on the DCC status flags.
| RX | Meaning |
|---|---|
| 0b0 |
No interrupt request generated by DTRRX. |
| 0b1 |
Interrupt request will be generated on RXfull == 1. |
If legacy COMMRX and COMMTX signals are implemented, then these are not affected by the value of this bit.
The reset behavior of this field is:
DCC interrupt request enable control for DTRTX. Enables a common COMMIRQ interrupt request to be signaled based on the DCC status flags.
| TX | Meaning |
|---|---|
| 0b0 |
No interrupt request generated by DTRTX. |
| 0b1 |
Interrupt request will be generated on TXfull == 0. |
If legacy COMMRX and COMMTX signals are implemented, then these are not affected by the value of this bit.
The reset behavior of this field is:
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, MDCCINT_EL1
(op0 = 0b10, op1 = 0b000, CRn = 0b0000, CRm = 0b0010, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif Halted() && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost()) && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG) then X{64}(t) = MDCCINT_EL1(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MDCCINT_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MDCCINT_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MDCCINT_EL1(); end;
MSR MDCCINT_EL1, <Xt>
(op0 = 0b10, op1 = 0b000, CRn = 0b0000, CRm = 0b0010, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif Halted() && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost()) && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG) then MDCCINT_EL1() = X{64}(t); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MDCCINT_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MDCCINT_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then MDCCINT_EL1() = X{64}(t); end;
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