Memory Attribute Indirection Register (EL1)
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL1.
AArch64 System register MAIR_EL1 bits [31:0] are architecturally mapped to AArch32 System register PRRR[31:0] when TTBCR.EAE == '0'.
AArch64 System register MAIR_EL1 bits [31:0] are architecturally mapped to AArch32 System register MAIR0[31:0] when TTBCR.EAE == '1'.
AArch64 System register MAIR_EL1 bits [63:32] are architecturally mapped to AArch32 System register NMRR[31:0] when TTBCR.EAE == '0'.
AArch64 System register MAIR_EL1 bits [63:32] are architecturally mapped to AArch32 System register MAIR1[31:0] when TTBCR.EAE == '1'.
This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to MAIR_EL1 are UNDEFINED.
MAIR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Attr7 | Attr6 | Attr5 | Attr4 | ||||||||||||||||||||||||||||
| Attr3 | Attr2 | Attr1 | Attr0 | ||||||||||||||||||||||||||||
MAIR_EL1 is permitted to be cached in a TLB.
Memory Attribute encoding.
When FEAT_AIE is implemented and stage 1 Attributes Index Extension is enabled and AttrIndx[3] in a Long descriptor format translation table entry is 0, or when FEAT_AIE is not implemented, AttrIndx[2:0] gives the value of <n> in Attr<n>.
When FEAT_AIE is implemented and stage 1 Attributes Index Extension is enabled and AttrIndx[3] in a Long descriptor format translation table entry is 1, see MAIR2_EL1.Attr
Attr is encoded as follows:
| Attr | Meaning | |
|---|---|---|
| '0000dd00' | Device memory. See encoding of 'dd' for the type of Device memory. | |
| '0000dd01' | If FEAT_XS is implemented: Device memory with the XS attribute set to 0. See encoding of 'dd' for the type of Device memory. Otherwise,UNPREDICTABLE. | |
| '0000dd1x' | UNPREDICTABLE. | |
| 'ooooiiii' | where oooo != 0000 and iiii != 0000 | Normal memory. See encoding of 'oooo' and 'iiii' for the type of Normal memory. |
| '01000000' | If FEAT_XS is implemented: Normal Inner Non-cacheable, Outer Non-cacheable memory with the XS attribute set to 0. Otherwise,UNPREDICTABLE. | |
| '10100000' | If FEAT_XS is implemented: Normal Inner Write-through Cacheable, Outer Write-through Cacheable, Read-Allocate, No-Write Allocate, Non-transient memory with the XS attribute set to 0. Otherwise,UNPREDICTABLE. | |
| '11110000' | If FEAT_MTE2 is implemented: Tagged Normal Inner Write-Back, Outer Write-Back, Read-Allocate, Write-Allocate Non-transient memory. Otherwise,UNPREDICTABLE. | |
| 'xxxx0000' | where xxxx != 0000 and xxxx != 0100 and xxxx != 1010 and xxxx != 1111 | UNPREDICTABLE. |
dd is encoded as follows:
| 'dd' | Meaning |
|---|---|
| '00' | Device-nGnRnE memory. |
| '01' | Device-nGnRE memory. |
| '10' | Device-nGRE memory. |
| '11' | Device-GRE memory. |
oooo is encoded as follows:
| 'oooo' | Meaning | |
|---|---|---|
| '0000' | See encoding of Attr. | |
| '00RW' | where RW != 00 | Normal memory, Outer Write-Through Transient. |
| '0100' | Normal memory, Outer Non-cacheable. | |
| '01RW' | where RW != 00 | Normal memory, Outer Write-Back Transient. |
| '10RW' | Normal memory, Outer Write-Through Non-transient. | |
| '11RW' | Normal memory, Outer Write-Back Non-transient. |
R encodes the Outer Read-Allocate policy and W encodes the Outer Write-Allocate policy.
iiii is encoded as follows:
| 'iiii' | Meaning | |
|---|---|---|
| '0000' | See encoding of Attr. | |
| '00RW' | where RW != 00 | Normal memory, Inner Write-Through Transient. |
| '0100' | Normal memory, Inner Non-cacheable. | |
| '01RW' | where RW != 00 | Normal memory, Inner Write-Back Transient. |
| '10RW' | Normal memory, Inner Write-Through Non-transient. | |
| '11RW' | Normal memory, Inner Write-Back Non-transient. |
R encodes the Inner Read-Allocate policy and W encodes the Inner Write-Allocate policy.
In oooo and iiii, R and W are encoded as follows:
| 'R' or 'W' | Meaning |
|---|---|
| '0' | No Allocate. |
| '1' | Allocate. |
When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name MAIR_EL1 or MAIR_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, MAIR_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0010, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TRVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().MAIR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x140); else X{64}(t) = MAIR_EL1(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X{64}(t) = MAIR_EL2(); else X{64}(t) = MAIR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MAIR_EL1(); end;
MSR MAIR_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0010, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().MAIR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x140) = X{64}(t); else MAIR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then MAIR_EL2() = X{64}(t); else MAIR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then MAIR_EL1() = X{64}(t); end;
MRS <Xt>, MAIR_EL12
(op0 = 0b11, op1 = 0b101, CRn = 0b1010, CRm = 0b0010, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x140); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X{64}(t) = MAIR_EL1(); else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = MAIR_EL1(); else Undefined(); end; end;
MSR MAIR_EL12, <Xt>
(op0 = 0b11, op1 = 0b101, CRn = 0b1010, CRm = 0b0010, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x140) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then MAIR_EL1() = X{64}(t); else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then MAIR_EL1() = X{64}(t); else Undefined(); end; end;
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