Extended Memory Attribute Indirection Register (EL3)
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a VMSAv8-64 or VMSAv9-128 translation table entry for stage 1 translations at EL1.
This register is present only when FEAT_AIE is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to MAIR2_EL3 are UNDEFINED.
MAIR2_EL3 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Attr7 | Attr6 | Attr5 | Attr4 | ||||||||||||||||||||||||||||
| Attr3 | Attr2 | Attr1 | Attr0 | ||||||||||||||||||||||||||||
Memory Attribute encoding.
When stage 1 Attributes Index Extension is enabled and AttrIndx[3] in a VMSAv8-64 or VMSAv9-128 translation table entry is 1, AttrIndx[2:0] gives the value of <n> in Attr<n>.
When stage 1 Attributes Index Extension is enabled and AttrIndx[3] in a VMSAv8-64 or VMSAv9-128 translation table entry is 0, see MAIR_EL3.Attr
Attr is encoded as follows:
| Attr | Meaning | |
|---|---|---|
| '0000dd00' | Device memory. See encoding of 'dd' for the type of Device memory. | |
| '0000dd01' | If FEAT_XS is implemented: Device memory with the XS attribute set to 0. See encoding of 'dd' for the type of Device memory. Otherwise,UNPREDICTABLE. | |
| '0000dd1x' | UNPREDICTABLE. | |
| 'ooooiiii' | where oooo != 0000 and iiii != 0000 | Normal memory. See encoding of 'oooo' and 'iiii' for the type of Normal memory. |
| '01000000' | If FEAT_XS is implemented: Normal Inner Non-cacheable, Outer Non-cacheable memory with the XS attribute set to 0. Otherwise,UNPREDICTABLE. | |
| '10100000' | If FEAT_XS is implemented: Normal Inner Write-through Cacheable, Outer Write-through Cacheable, Read-Allocate, No-Write Allocate, Non-transient memory with the XS attribute set to 0. Otherwise,UNPREDICTABLE. | |
| '11110000' | If FEAT_MTE2 is implemented: Tagged Normal Inner Write-Back, Outer Write-Back, Read-Allocate, Write-Allocate Non-transient memory. Otherwise,UNPREDICTABLE. | |
| 'xxxx0000' | where xxxx != 0000 and xxxx != 0100 and xxxx != 1010 and xxxx != 1111 | UNPREDICTABLE. |
dd is encoded as follows:
| 'dd' | Meaning |
|---|---|
| '00' | Device-nGnRnE memory. |
| '01' | Device-nGnRE memory. |
| '10' | Device-nGRE memory. |
| '11' | Device-GRE memory. |
oooo is encoded as follows:
| 'oooo' | Meaning | |
|---|---|---|
| '0000' | See encoding of Attr. | |
| '00RW' | where RW != 00 | Normal memory, Outer Write-Through Transient. |
| '0100' | Normal memory, Outer Non-cacheable. | |
| '01RW' | where RW != 00 | Normal memory, Outer Write-Back Transient. |
| '10RW' | Normal memory, Outer Write-Through Non-transient. | |
| '11RW' | Normal memory, Outer Write-Back Non-transient. |
R encodes the Outer Read-Allocate policy and W encodes the Outer Write-Allocate policy.
iiii is encoded as follows:
| 'iiii' | Meaning | |
|---|---|---|
| '0000' | See encoding of Attr. | |
| '00RW' | where RW != 00 | Normal memory, Inner Write-Through Transient. |
| '0100' | Normal memory, Inner Non-cacheable. | |
| '01RW' | where RW != 00 | Normal memory, Inner Write-Back Transient. |
| '10RW' | Normal memory, Inner Write-Through Non-transient. | |
| '11RW' | Normal memory, Inner Write-Back Non-transient. |
R encodes the Inner Read-Allocate policy and W encodes the Inner Write-Allocate policy.
In oooo and iiii, R and W are encoded as follows:
| 'R' or 'W' | Meaning |
|---|---|
| '0' | No Allocate. |
| '1' | Allocate. |
When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, MAIR2_EL3
(op0 = 0b11, op1 = 0b110, CRn = 0b1010, CRm = 0b0001, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_AIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = MAIR2_EL3(); end;
MSR MAIR2_EL3, <Xt>
(op0 = 0b11, op1 = 0b110, CRn = 0b1010, CRm = 0b0001, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_AIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3().MAIR2_EL3 == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else MAIR2_EL3() = X{64}(t); end; end;
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