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LORSA_EL1

LORegion Start Address (EL1)

Indicates whether the current LORegion descriptor selected by LORC_EL1.DS is enabled, and holds the physical address of the start of the LORegion.

Configuration

This register is present only when FEAT_LOR is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to LORSA_EL1 are UNDEFINED.

This register is RES0 if any of the following apply:

Attributes

LORSA_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0SA
SARES0RLValid

Any of the fields in this register are permitted to be cached in a TLB.

Bits [63:56]:

Reserved, RES0.

SA, bits [55:16]:

SA encoding when FEAT_D128 is implemented

3938373635343332
313029282726252423222120191817161514131211109876543210
SA
SA

SA, bits [39:0]:

Bits [55:16] of the start physical address of the LORegion described in the current LORegion descriptor selected by LORC_EL1.DS.

Bits[15:0] of this address are 0x0000.

For implementations with fewer than 56 physical address bits, the corresponding upper bits of this field are RES0.

The reset behavior of this field is:

  • On a Warm reset, this field resets to an architecturally UNKNOWN value.

SA encoding when FEAT_LPA is implemented and FEAT_D128 is not implemented

3938373635343332
313029282726252423222120191817161514131211109876543210
RES0SA
SA

Bits [39:36]:

Reserved, RES0.

SA, bits [35:0]:

Bits [51:16] of the start physical address of the LORegion described in the current LORegion descriptor selected by LORC_EL1.DS.

Bits[15:0] of this address are 0x0000.

For implementations with fewer than 52 physical address bits, the corresponding upper bits of this field are RES0.

The reset behavior of this field is:

  • On a Warm reset, this field resets to an architecturally UNKNOWN value.

SA encoding when FEAT_LPA is not implemented

3938373635343332
313029282726252423222120191817161514131211109876543210
RES0
SA

Bits [39:32]:

Reserved, RES0.

SA, bits [31:0]:

Bits [47:16] of the start physical address of the LORegion described in the current LORegion descriptor selected by LORC_EL1.DS.

Bits[15:0] of this address are 0x0000.

For implementations with fewer than 48 physical address bits, the corresponding upper bits of this field are RES0.

The reset behavior of this field is:

  • On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [15:2]:

Reserved, RES0.

RL, bit [1] when FEAT_LORRL is implemented:

Configures the PA space that can match the LORegion.

RLMeaning
0b0

Only Non-secure PA space addresses can match this region.

0b1

Non-secure and Realm PA space addresses can match this region.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Valid, bit [0]:

Indicates whether the current LORegion descriptor is enabled.

ValidMeaning
0b0

LORegion descriptor is disabled.

0b1

LORegion descriptor is enabled.

The reset behavior of this field is:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, LORSA_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0100, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_LOR) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().TLOR == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && SCR_EL3().NS == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TLOR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().LORSA_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TLOR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = LORSA_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TLOR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = LORSA_EL1(); end; elsif PSTATE.EL == EL3 then if SCR_EL3().NS == '0' then Undefined(); else X{64}(t) = LORSA_EL1(); end; end;

MSR LORSA_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b1010, CRm = 0b0100, op2 = 0b000)

if !(IsFeatureImplemented(FEAT_LOR) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().TLOR == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && SCR_EL3().NS == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TLOR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().LORSA_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TLOR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else LORSA_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TLOR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else LORSA_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if SCR_EL3().NS == '0' then Undefined(); else LORSA_EL1() = X{64}(t); end; end;

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