ICV_PPI_SACTIVER<n>_EL1 | Jon's Arm Reference

AArch64 System register ICV_PPI_SACTIVER<n>_EL1 bits [63:0] are architecturally mapped to AArch64 System register ICH_PPI_ACTIVER<n>_EL2[63:0].

AArch64 System register ICV_PPI_SACTIVER<n>_EL1 bits [63:0] are architecturally mapped to AArch64 System register ICV_PPI_CACTIVER<n>_EL1[63:0].

This register is present only when FEAT_GCIE is implemented, EL2 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to ICV_PPI_SACTIVER<n>_EL1 are UNDEFINED.

Attributes

Field descriptions

ACTIVE<x>, bit [x], for x = 63 to 0:

PPI <(n * 64) + x> Active state.

Reads return the Active state of the PPI.

Writing 1 sets the Active state of the PPI. Writing 0 has no effect.

ACTIVE<x>	Meaning
0b0	Inactive
0b1	Active

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

Accessing this field has the following behavior:

When !IsPPIImplemented((n * 64) + x), access to this field is RAZ/WI.
Otherwise, access to this field is W1S.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICC_PPI_SACTIVER<n>_EL1 ; Where n = 0-1

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1101, op2 = 0b01:n[0])

let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGRTR_EL2().ICC_PPI_ACTIVERn_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_PPI_SACTIVER_EL1(n); else X{64}(t) = ICC_PPI_SACTIVER_EL1(n); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICC_PPI_SACTIVER_EL1(n); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_PPI_SACTIVER_EL1(n); end;

MSR ICC_PPI_SACTIVER<n>_EL1, <Xt> ; Where n = 0-1

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1101, op2 = 0b01:n[0])

let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGWTR_EL2().ICC_PPI_ACTIVERn_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_PPI_SACTIVER_EL1(n) = X{64}(t); else ICC_PPI_SACTIVER_EL1(n) = X{64}(t); end; elsif PSTATE.EL == EL2 then ICC_PPI_SACTIVER_EL1(n) = X{64}(t); elsif PSTATE.EL == EL3 then ICC_PPI_SACTIVER_EL1(n) = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE63	ACTIVE62	ACTIVE61	ACTIVE60	ACTIVE59	ACTIVE58	ACTIVE57	ACTIVE56	ACTIVE55	ACTIVE54	ACTIVE53	ACTIVE52	ACTIVE51	ACTIVE50	ACTIVE49	ACTIVE48	ACTIVE47	ACTIVE46	ACTIVE45	ACTIVE44	ACTIVE43	ACTIVE42	ACTIVE41	ACTIVE40	ACTIVE39	ACTIVE38	ACTIVE37	ACTIVE36	ACTIVE35	ACTIVE34	ACTIVE33	ACTIVE32
ACTIVE31	ACTIVE30	ACTIVE29	ACTIVE28	ACTIVE27	ACTIVE26	ACTIVE25	ACTIVE24	ACTIVE23	ACTIVE22	ACTIVE21	ACTIVE20	ACTIVE19	ACTIVE18	ACTIVE17	ACTIVE16	ACTIVE15	ACTIVE14	ACTIVE13	ACTIVE12	ACTIVE11	ACTIVE10	ACTIVE9	ACTIVE8	ACTIVE7	ACTIVE6	ACTIVE5	ACTIVE4	ACTIVE3	ACTIVE2	ACTIVE1	ACTIVE0

ICV_PPI_SACTIVER<n>_EL1, n = 0 - 1

Configuration

Attributes

Field descriptions

ACTIVE<x>, bit [x], for x = 63 to 0:

Access Instructions