ICV_PPI_PRIORITYR<n>_EL1 | Jon's Arm Reference

AArch64 System register ICV_PPI_PRIORITYR<n>_EL1 bits [63:0] are architecturally mapped to AArch64 System register ICH_PPI_PRIORITYR<n>_EL2[63:0].

This register is present only when FEAT_GCIE is implemented, EL2 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to ICV_PPI_PRIORITYR<n>_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:61, 55:53, 47:45, 39:37, 31:29, 23:21, 15:13, 7:5]:

PRIORITY<x>, bits [60:56, 52:48, 44:40, 36:32, 28:24, 20:16, 12:8, 4:0], for x = 7 to 0, where each field is 5 bits wide :

The priority of PPI <(n * 8) + x>.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

Accessing this field has the following behavior:

When !IsPPIImplemented((n * 8) + x), access to this field is RAZ/WI.
Otherwise, access to this field is RW.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICC_PPI_PRIORITYR<n>_EL1 ; Where n = 0-15

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b111:n[3], op2 = n[2:0])

let n:integer = UInt(CRm[0] :: op2[2:0]); if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGRTR_EL2().ICC_PPI_PRIORITYRn_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_PPI_PRIORITYR_EL1(n); else X{64}(t) = ICC_PPI_PRIORITYR_EL1(n); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICC_PPI_PRIORITYR_EL1(n); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_PPI_PRIORITYR_EL1(n); end;

MSR ICC_PPI_PRIORITYR<n>_EL1, <Xt> ; Where n = 0-15

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b111:n[3], op2 = n[2:0])

let n:integer = UInt(CRm[0] :: op2[2:0]); if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGWTR_EL2().ICC_PPI_PRIORITYRn_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_PPI_PRIORITYR_EL1(n) = X{64}(t); else ICC_PPI_PRIORITYR_EL1(n) = X{64}(t); end; elsif PSTATE.EL == EL2 then ICC_PPI_PRIORITYR_EL1(n) = X{64}(t); elsif PSTATE.EL == EL3 then ICC_PPI_PRIORITYR_EL1(n) = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0			PRIORITY7					RES0			PRIORITY6					RES0			PRIORITY5					RES0			PRIORITY4
RES0			PRIORITY3					RES0			PRIORITY2					RES0			PRIORITY1					RES0			PRIORITY0

ICV_PPI_PRIORITYR<n>_EL1, n = 0 - 15

Configuration

Attributes

Field descriptions

Bits [63:61, 55:53, 47:45, 39:37, 31:29, 23:21, 15:13, 7:5]:

PRIORITY<x>, bits [60:56, 52:48, 44:40, 36:32, 28:24, 20:16, 12:8, 4:0], for x = 7 to 0, where each field is 5 bits wide :

Access Instructions