Interrupt Controller Virtual End Of Interrupt Register 1
A PE writes to this register to inform the CPU interface that it has completed the processing of the specified virtual Group 1 interrupt.
AArch64 System register ICV_EOIR1_EL1 bits [31:0] performs the same function as AArch32 System register ICV_EOIR1[31:0].
This register is present only when (GICv3 is implemented or FEAT_GCIE_LEGACY is implemented), EL2 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to ICV_EOIR1_EL1 are UNDEFINED.
ICV_EOIR1_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | INTID | ||||||||||||||||||||||||||||||
Reserved, RES0.
The INTID from the corresponding ICV_IAR1_EL1 access.
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICV_CTLR_EL1.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
If the ICV_CTLR_EL1.EOImode bit is 0, a write to this register drops the priority for the virtual interrupt, and also deactivates the virtual interrupt.
If the ICV_CTLR_EL1.EOImode bit is 1, a write to this register only drops the priority for the virtual interrupt. Software must write to ICV_DIR_EL1 to deactivate the virtual interrupt.
A write to this register must correspond to the most recent valid read by this vPE from a Virtual Interrupt Acknowledge Register, and must correspond to the INTID that was read from ICV_IAR1_EL1, otherwise the system behavior is UNPREDICTABLE. A valid read is a read that returns a valid INTID that is not a special INTID.
Accesses to this register use the following encodings in the System register encoding space:
MSR ICC_EOIR1_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1100, op2 = 0b001)
if !((IsFeatureImplemented(FEAT_GICv3) || IsFeatureImplemented(FEAT_GCIE_LEGACY)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) && (ICH_VCTLR_EL2().V3 == '0' || !EL2Enabled() || !(ICH_HCR_EL2().TALL1 == '1' || HCR_EL2().IMO == '1')) then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TALL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_EOIR1_EL1() = X{64}(t); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_EOIR1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_EOIR1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) then Undefined(); elsif ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICC_EOIR1_EL1() = X{64}(t); end; end;
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