Interrupt Controller EL1 Virtual Control Register
Controls behavior of the CPU interface in the Virtual Interrupt Domain.
This register is present only when FEAT_GCIE is implemented, EL2 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to ICV_CR0_EL1 are UNDEFINED.
ICV_CR0_EL1 is a 64-bit register.
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| RES0 | |||||||||||||||||||||||||||||||
| RES0 | LINK_IDLE | LINK | EN | ||||||||||||||||||||||||||||
Reserved, RES0.
Whether the link between the CPU interface and the IRI is in the process of connecting or disconnecting.
| LINK_IDLE | Meaning |
|---|---|
| 0b0 |
The link between the CPU interface and the IRI is in the process of connecting or disconnecting. |
| 0b1 |
The link between the CPU interface and the IRI is not in the process of connecting or disconnecting. |
Access to this field is RAO/WI.
Whether the link between the CPU interface and the IRI is connected.
| LINK | Meaning |
|---|---|
| 0b0 |
The link between the CPU interface and the IRI is disconnected. |
| 0b1 |
The link between the CPU interface and the IRI is connected. |
Access to this field is RAO/WI.
Enable interrupts for the Interrupt Domain.
When this field is 0, there is no HPPI of Sufficient priority for the Interrupt Domain.
| EN | Meaning |
|---|---|
| 0b0 |
Disabled. |
| 0b1 |
Enabled. |
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_CR0_EL1
(op0 = 0b11, op1 = 0b001, CRn = 0b1100, CRm = 0b0000, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGRTR_EL2().ICC_CR0_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_CR0_EL1(); elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CR0_EL1_S(); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_RL(); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_NS(); else Undefined(); end; else X{64}(t) = ICC_CR0_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CR0_EL1_S(); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_RL(); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_NS(); else Undefined(); end; else X{64}(t) = ICC_CR0_EL1(); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CR0_EL1_S(); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_RL(); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_NS(); else Undefined(); end; end;
MSR ICC_CR0_EL1, <Xt>
(op0 = 0b11, op1 = 0b001, CRn = 0b1100, CRm = 0b0000, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGWTR_EL2().ICC_CR0_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_CR0_EL1() = X{64}(t); elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_CR0_EL1_S() = X{64}(t); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_RL() = X{64}(t); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_NS() = X{64}(t); else Undefined(); end; else ICC_CR0_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_CR0_EL1_S() = X{64}(t); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_RL() = X{64}(t); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_NS() = X{64}(t); else Undefined(); end; else ICC_CR0_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then ICC_CR0_EL1_S() = X{64}(t); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_RL() = X{64}(t); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_NS() = X{64}(t); else Undefined(); end; end;
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