Interrupt Controller PPI Hide Virtual Interrupt Registers
Controls whether an implemented PPI is hidden from the Virtual Interrupt Domain.
This register is present only when FEAT_GCIE is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented. Otherwise, direct accesses to ICH_PPI_HVIR<n>_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_PPI_HVIR<n>_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HVI63 | HVI62 | HVI61 | HVI60 | HVI59 | HVI58 | HVI57 | HVI56 | HVI55 | HVI54 | HVI53 | HVI52 | HVI51 | HVI50 | HVI49 | HVI48 | HVI47 | HVI46 | HVI45 | HVI44 | HVI43 | HVI42 | HVI41 | HVI40 | HVI39 | HVI38 | HVI37 | HVI36 | HVI35 | HVI34 | HVI33 | HVI32 |
| HVI31 | HVI30 | HVI29 | HVI28 | HVI27 | HVI26 | HVI25 | HVI24 | HVI23 | HVI22 | HVI21 | HVI20 | HVI19 | HVI18 | HVI17 | HVI16 | HVI15 | HVI14 | HVI13 | HVI12 | HVI11 | HVI10 | HVI9 | HVI8 | HVI7 | HVI6 | HVI5 | HVI4 | HVI3 | HVI2 | HVI1 | HVI0 |
Hide virtual PPI <(n * 64) + x> in the Virtual Interrupt Domain.
When a virtual PPI is hidden, direct reads and writes to ICV_ register fields corresponding to the virtual PPI are RAZ/WI.
| HVI<x> | Meaning |
|---|---|
| 0b0 |
Accesses to ICV_ register fields corresponding to virtual PPI <(n * 64) + x> are not affected by this control. |
| 0b1 | Direct reads and writes to ICV_ register fields corresponding to virtual PPI <(n * 64) + x> are RAZ/WI. The Effective value of ICH_PPI_DVIR<n>_EL2.DVI<x> is 0. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICH_PPI_HVIR<n>_EL2 ; Where n = 0-1
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b0111, op2 = 0b00:n[0])
let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then X{64}(t) = NVMem(0xC00 + (8 * n)); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICH_PPI_HVIR_EL2(n); elsif PSTATE.EL == EL3 then X{64}(t) = ICH_PPI_HVIR_EL2(n); end;
MSR ICH_PPI_HVIR<n>_EL2, <Xt> ; Where n = 0-1
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b0111, op2 = 0b00:n[0])
let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then NVMem(0xC00 + (8 * n)) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then ICH_PPI_HVIR_EL2(n) = X{64}(t); elsif PSTATE.EL == EL3 then ICH_PPI_HVIR_EL2(n) = X{64}(t); end;
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