Interrupt Controller Virtual Interrupt Enable Registers
Access to Enable state for virtual PPIs.
AArch64 System register ICH_PPI_ENABLER<n>_EL2 bits [63:0] are architecturally mapped to AArch64 System register ICV_PPI_ENABLER<n>_EL1[63:0].
This register is present only when FEAT_GCIE is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented. Otherwise, direct accesses to ICH_PPI_ENABLER<n>_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_PPI_ENABLER<n>_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EN63 | EN62 | EN61 | EN60 | EN59 | EN58 | EN57 | EN56 | EN55 | EN54 | EN53 | EN52 | EN51 | EN50 | EN49 | EN48 | EN47 | EN46 | EN45 | EN44 | EN43 | EN42 | EN41 | EN40 | EN39 | EN38 | EN37 | EN36 | EN35 | EN34 | EN33 | EN32 |
| EN31 | EN30 | EN29 | EN28 | EN27 | EN26 | EN25 | EN24 | EN23 | EN22 | EN21 | EN20 | EN19 | EN18 | EN17 | EN16 | EN15 | EN14 | EN13 | EN12 | EN11 | EN10 | EN9 | EN8 | EN7 | EN6 | EN5 | EN4 | EN3 | EN2 | EN1 | EN0 |
Virtual PPI <(n * 64) + x> Enable.
Accessing this field has the following behavior:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICH_PPI_ENABLER<n>_EL2 ; Where n = 0-1
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1010, op2 = 0b01:n[0])
let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then X{64}(t) = NVMem(0xB50 + (8 * n)); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICH_PPI_ENABLER_EL2(n); elsif PSTATE.EL == EL3 then X{64}(t) = ICH_PPI_ENABLER_EL2(n); end;
MSR ICH_PPI_ENABLER<n>_EL2, <Xt> ; Where n = 0-1
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1010, op2 = 0b01:n[0])
let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then NVMem(0xB50 + (8 * n)) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then ICH_PPI_ENABLER_EL2(n) = X{64}(t); elsif PSTATE.EL == EL3 then ICH_PPI_ENABLER_EL2(n) = X{64}(t); end;
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