ICH_PPI_DVIR<n>_EL2 | Jon's Arm Reference

This register is present only when FEAT_GCIE is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented. Otherwise, direct accesses to ICH_PPI_DVIR<n>_EL2 are UNDEFINED.

Attributes

Field descriptions

DVI<x>, bit [x], for x = 63 to 0:

Controls whether physical PPI <(n * 64) + x> is directly injected to a virtual PPI in the Virtual Interrupt Domain.

DVI<x>	Meaning
0b0	The physical PPI is not directly injected as a virtual PPI.
0b1	The physical PPI is directly injected as a virtual PPI.

The Effective value of DVI<(n * 64) + x> is 0 if any of the following are true:

The corresponding physical PPI is not assigned to Current Physical Interrupt Domain.
The corresponding physical PPI is assigned to the EL3 Interrupt Domain.
The corresponding physical PPI is assigned to the Secure Interrupt Domain and SCR_EL3.EEL2 is 0.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

Accessing this field has the following behavior:

When !IsPPIImplemented((n * 64) + x), access to this field is RAZ/WI.
Access to this field is RAZ/WI if all the following are true:
- !IsPPIAssignedToCurrentDomain((n * 64) + x).
- PSTATE.EL IN {EL2, EL1}.
Otherwise, access to this field is RW.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICH_PPI_DVIR<n>_EL2 ; Where n = 0-1

(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1010, op2 = 0b00:n[0])

let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then X{64}(t) = NVMem(0xB40 + (8 * n)); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICH_PPI_DVIR_EL2(n); elsif PSTATE.EL == EL3 then X{64}(t) = ICH_PPI_DVIR_EL2(n); end;

MSR ICH_PPI_DVIR<n>_EL2, <Xt> ; Where n = 0-1

(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1010, op2 = 0b00:n[0])

let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then NVMem(0xB40 + (8 * n)) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then ICH_PPI_DVIR_EL2(n) = X{64}(t); elsif PSTATE.EL == EL3 then ICH_PPI_DVIR_EL2(n) = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DVI63	DVI62	DVI61	DVI60	DVI59	DVI58	DVI57	DVI56	DVI55	DVI54	DVI53	DVI52	DVI51	DVI50	DVI49	DVI48	DVI47	DVI46	DVI45	DVI44	DVI43	DVI42	DVI41	DVI40	DVI39	DVI38	DVI37	DVI36	DVI35	DVI34	DVI33	DVI32
DVI31	DVI30	DVI29	DVI28	DVI27	DVI26	DVI25	DVI24	DVI23	DVI22	DVI21	DVI20	DVI19	DVI18	DVI17	DVI16	DVI15	DVI14	DVI13	DVI12	DVI11	DVI10	DVI9	DVI8	DVI7	DVI6	DVI5	DVI4	DVI3	DVI2	DVI1	DVI0

ICH_PPI_DVIR<n>_EL2, n = 0 - 1

Configuration

Attributes

Field descriptions

DVI<x>, bit [x], for x = 63 to 0:

Access Instructions