Interrupt Controller Virtual Interrupt Active Registers
Access to Active state for virtual PPIs.
AArch64 System register ICH_PPI_ACTIVER<n>_EL2 bits [63:0] are architecturally mapped to AArch64 System register ICV_PPI_CACTIVER<n>_EL1[63:0].
AArch64 System register ICH_PPI_ACTIVER<n>_EL2 bits [63:0] are architecturally mapped to AArch64 System register ICV_PPI_SACTIVER<n>_EL1[63:0].
This register is present only when FEAT_GCIE is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented. Otherwise, direct accesses to ICH_PPI_ACTIVER<n>_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_PPI_ACTIVER<n>_EL2 is a 64-bit register.
Virtual PPI <(n * 64) + x> Active state.
| ACTIVE<x> | Meaning |
|---|---|
| 0b0 |
Inactive |
| 0b1 |
Active |
The reset behavior of this field is:
Accessing this field has the following behavior:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICH_PPI_ACTIVER<n>_EL2 ; Where n = 0-1
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1010, op2 = 0b11:n[0])
let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then X{64}(t) = NVMem(0xB30 + (8 * n)); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICH_PPI_ACTIVER_EL2(n); elsif PSTATE.EL == EL3 then X{64}(t) = ICH_PPI_ACTIVER_EL2(n); end;
MSR ICH_PPI_ACTIVER<n>_EL2, <Xt> ; Where n = 0-1
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1010, op2 = 0b11:n[0])
let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then NVMem(0xB30 + (8 * n)) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then ICH_PPI_ACTIVER_EL2(n) = X{64}(t); elsif PSTATE.EL == EL3 then ICH_PPI_ACTIVER_EL2(n) = X{64}(t); end;
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