Interrupt Controller Hypervisor Highest Priority Pending Interrupt Register
Reports the HPPI for the Virtual Interrupt Domain.
AArch64 System register ICH_HPPIR_EL2 bits [63:0] are architecturally mapped to AArch64 System register ICV_HPPIR_EL1[63:0].
This register is present only when FEAT_GCIE is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented. Otherwise, direct accesses to ICH_HPPIR_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_HPPIR_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | HPPIV | ||||||||||||||||||||||||||||||
| TYPE | RES0 | ID | |||||||||||||||||||||||||||||
Reserved, RES0.
HPPI valid.
There is an HPPI with Sufficient priority for the Interrupt Domain.
| HPPIV | Meaning |
|---|---|
| 0b0 |
Invalid: There is no HPPI with Sufficient priority for the Interrupt Domain. |
| 0b1 |
VALID: There is an HPPI with Sufficient priority for the Interrupt Domain. |
If ICH_HPPIR_EL2.HPPIV is 1, ID and TYPE together form the INTID of the HPPI for the Interrupt Domain.
The encoding of this field depends on the value of HPPIV as described below:
If ICH_HPPIR_EL2.HPPIV is 0, TYPE is RES0.
If ICH_HPPIR_EL2.HPPIV is 1, TYPE specifies the Type of the interrupt.
| TYPE | Meaning |
|---|---|
| 0b001 |
PPI |
| 0b010 |
LPI |
| 0b011 |
SPI |
Values not defined above are reserved.
Reserved, RES0.
The encoding of this field depends on the value of HPPIV as described below:
If ICH_HPPIR_EL2.HPPIV is 0, ID is RES0.
If ICH_HPPIR_EL2.HPPIV is 1, ID specifies the interrupt ID.
This register is Read-only.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICH_HPPIR_EL2
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1000, op2 = 0b101)
if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICH_HPPIR_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = ICH_HPPIR_EL2(); end;
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