ICH_HFGWTR_EL2

Hypervisor GIC Fine-Grained Write Trap Register

Provides controls for traps of MSR writes of GIC System registers.

Configuration

This register is present only when FEAT_GCIE is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented. Otherwise, direct accesses to ICH_HFGWTR_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

ICH_HFGWTR_EL2 is a 64-bit register.

Field descriptions

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0											ICC_PPI_ACTIVERn_EL1	ICC_PPI_PRIORITYRn_EL1	ICC_PPI_PENDRn_EL1	ICC_PPI_ENABLERn_EL1	RES0										ICC_ICSR_EL1	ICC_PCR_EL1	RES0		ICC_CR0_EL1	RES0	ICC_APR_EL1

Bits [63:21]:

Reserved, RES0.

ICC_PPI_ACTIVERn_EL1, bit [20]:

Trap MSR writes of ICC_PPI_CACTIVER<n>_EL1, ICC_PPI_SACTIVER<n>_EL1, ICV_PPI_CACTIVER<n>_EL1 and ICV_PPI_SACTIVER<n>_EL1 at EL1 using AArch64 to EL2.

ICC_PPI_ACTIVERn_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MSR writes of the specified registers at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MSR writes of the specified registers are not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

ICC_PPI_PRIORITYRn_EL1, bit [19]:

Trap MSR writes of ICC_PPI_PRIORITYR<n>_EL1 and ICV_PPI_PRIORITYR<n>_EL1 at EL1 using AArch64 to EL2.

ICC_PPI_PRIORITYRn_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MSR writes of the specified registers at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MSR writes of the specified registers are not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

ICC_PPI_PENDRn_EL1, bit [18]:

Trap MSR writes of ICC_PPI_CPENDR<n>_EL1, ICC_PPI_SPENDR<n>_EL1 ICV_PPI_CPENDR<n>_EL1 and ICV_PPI_SPENDR<n>_EL1 at EL1 using AArch64 to EL2.

ICC_PPI_PENDRn_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MSR writes of the specified registers at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MSR writes of the specified registers are not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

ICC_PPI_ENABLERn_EL1, bit [17]:

Trap MSR writes of ICC_PPI_ENABLER<n>_EL1 and ICV_PPI_ENABLER<n>_EL1 at EL1 using AArch64 to EL2.

ICC_PPI_ENABLERn_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MSR writes of the specified registers at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MSR writes of the specified registers are not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

Bits [16:7]:

Reserved, RES0.

ICC_ICSR_EL1, bit [6]:

Trap MSR writes of ICC_ICSR_EL1 at EL1 using AArch64 to EL2.

ICC_ICSR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MSR writes of the specified registers at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MSR writes of the specified registers are not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

ICC_PCR_EL1, bit [5]:

Trap MSR writes of ICC_PCR_EL1 and ICV_PCR_EL1 at EL1 using AArch64 to EL2.

ICC_PCR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MSR writes of the specified registers at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MSR writes of the specified registers are not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

Bits [4:3]:

Reserved, RES0.

ICC_CR0_EL1, bit [2]:

Trap MSR writes of ICC_CR0_EL1 and ICV_CR0_EL1 at EL1 using AArch64 to EL2.

ICC_CR0_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MSR writes of the specified registers at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MSR writes of the specified registers are not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

Bit [1]:

Reserved, RES0.

ICC_APR_EL1, bit [0]:

Trap MSR writes of ICC_APR_EL1 and ICV_APR_EL1 at EL1 using AArch64 to EL2.

ICC_APR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MSR writes of the specified registers at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MSR writes of the specified registers are not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICH_HFGWTR_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1001, op2 = 0b110)

if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then X{64}(t) = NVMem(0xB20); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICH_HFGWTR_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = ICH_HFGWTR_EL2(); end;

MSR ICH_HFGWTR_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1001, op2 = 0b110)

if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then NVMem(0xB20) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then ICH_HFGWTR_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then ICH_HFGWTR_EL2() = X{64}(t); end;

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