ICH_HFGITR_EL2

Hypervisor GIC Fine-Grained Instruction Trap Register

Provides instruction trap controls for GIC System instructions.

Configuration

This register is present only when FEAT_GCIE is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented. Otherwise, direct accesses to ICH_HFGITR_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

ICH_HFGITR_EL2 is a 64-bit register.

Field descriptions

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																					GICRCDNMIA	GICRCDIA	GICCDDI	GICCDEOI	GICCDHM	GICCDRCFG	GICCDPEND	GICCDAFF	GICCDPRI	GICCDDIS	GICCDEN

Bits [63:11]:

Reserved, RES0.

GICRCDNMIA, bit [10]:

Trap execution of GICR CDNMIA at EL1 to EL2.

GICRCDNMIA	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GICR CDNMIA at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GICR CDNMIA is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

GICRCDIA, bit [9]:

Trap execution of GICR CDIA at EL1 to EL2.

GICRCDIA	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GICR CDIA at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GICR CDIA is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

GICCDDI, bit [8]:

Trap execution of GIC CDDI at EL1 to EL2.

GICCDDI	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GIC CDDI at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GIC CDDI is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

GICCDEOI, bit [7]:

Trap execution of GIC CDEOI at EL1 to EL2.

GICCDEOI	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GIC CDEOI at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GIC CDEOI is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

GICCDHM, bit [6]:

Trap execution of GIC CDHM at EL1 to EL2.

GICCDHM	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GIC CDHM at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GIC CDHM is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

GICCDRCFG, bit [5]:

Trap execution of GIC CDRCFG at EL1 to EL2.

GICCDRCFG	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GIC CDRCFG at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GIC CDRCFG is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

GICCDPEND, bit [4]:

Trap execution of GIC CDPEND at EL1 to EL2.

GICCDPEND	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GIC CDPEND at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GIC CDPEND is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

GICCDAFF, bit [3]:

Trap execution of GIC CDAFF at EL1 to EL2.

GICCDAFF	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GIC CDAFF at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GIC CDAFF is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

GICCDPRI, bit [2]:

Trap execution of GIC CDPRI at EL1 to EL2.

GICCDPRI	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GIC CDPRI at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GIC CDPRI is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

GICCDDIS, bit [1]:

Trap execution of GIC CDDIS at EL1 to EL2.

GICCDDIS	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GIC CDDIS at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GIC CDDIS is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

GICCDEN, bit [0]:

Trap execution of GIC CDEN at EL1 to EL2.

GICCDEN	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then execution of GIC CDEN at EL1 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b1	Execution of GIC CDEN is not trapped by this mechanism.

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICH_HFGITR_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1001, op2 = 0b111)

if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then X{64}(t) = NVMem(0xB10); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICH_HFGITR_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = ICH_HFGITR_EL2(); end;

MSR ICH_HFGITR_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1001, op2 = 0b111)

if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then NVMem(0xB10) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then ICH_HFGITR_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then ICH_HFGITR_EL2() = X{64}(t); end;

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