Interrupt Controller Virtual Context Register
Selects the current resident VPE.
This register is present only when FEAT_GCIE is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented. Otherwise, direct accesses to ICH_CONTEXTR_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_CONTEXTR_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| V | F | IRICHPPIDIS | DB | DBPM | RES0 | VPE | |||||||||||||||||||||||||
| RES0 | VM | ||||||||||||||||||||||||||||||
Indicates whether a VPE is currently resident.
If EL2 is not enabled in the Security state identified by SCR_EL3.{NSE,NS}, the Effective value of this field is 0.
| V | Meaning |
|---|---|
| 0b0 |
No VPE is resident. |
| 0b1 |
A VPE is resident. |
The reset behavior of this field is:
Indicates whether the last write that set V to 1 succeeded in making a VPE resident.
| F | Meaning |
|---|---|
| 0b0 |
Success |
| 0b1 |
Fault |
The reset behavior of this field is:
Specifies whether the candidate HPPI presented by the IRI for the resident VPE is considered when selecting the HPPI for the Virtual Interrupt Domain.
When V is 0, this field is IGNORED.
| IRICHPPIDIS | Meaning |
|---|---|
| 0b0 |
The CPU interface considers both the virtual PPIs and the candidate HPPI presented by the IRI when determining the HPPI for the Virtual Interrupt Domain. |
| 0b1 |
The CPU interface only considers the virtual PPIs when determining the HPPI for the Virtual Interrupt Domain. |
The reset behavior of this field is:
Specifies whether a doorbell interrupt is requested when making a VPE non-resident.
| DB | Meaning |
|---|---|
| 0b0 |
No doorbell requested. |
| 0b1 |
Doorbell requested. |
On a write that changes V from 1 to 0, this field specifies whether a doorbell interrupt is requested for the previously resident VPE.
For all other writes, this field is IGNORED.
On reads, this field is RAZ.
If the current value of SCR_EL3.{NSE,NS} is different from the value at the time the VPE was made resident, this field behaves as if set to 0.
This field has no effect if EL2 is not enabled in the Security state identified by SCR_EL3.{NSE,NS}.
The reset behavior of this field is:
Doorbell priority mask.
On a write that changes V from 1 to 0, when DB is written as 1, this field specifies the minimum priority for a virtual interrupt to trigger the VPE's doorbell.
For all other writes, this field is IGNORED.
On reads, this field is RAZ.
This field has no effect if EL2 is not enabled in the Security state identified by SCR_EL3.{NSE,NS}.
The reset behavior of this field is:
Reserved, RES0.
When V is 1, identifies the resident VPE.
When V is 0, this field is IGNORED.
This field has no effect if EL2 is not enabled in the Security state identified by SCR_EL3.{NSE,NS}.
The reset behavior of this field is:
Reserved, RES0.
When V is 1, identifies the resident VM.
When V is 0, this field is IGNORED.
This field has no effect if EL2 is not enabled in the Security state identified by SCR_EL3.{NSE,NS}.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICH_CONTEXTR_EL2
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1011, op2 = 0b110)
if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then X{64}(t) = NVMem(0xB08); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICH_CONTEXTR_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = ICH_CONTEXTR_EL2(); end;
MSR ICH_CONTEXTR_EL2, <Xt>
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1011, op2 = 0b110)
if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then NVMem(0xB08) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then ICH_CONTEXTR_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then ICH_CONTEXTR_EL2() = X{64}(t); end;
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