Interrupt Controller Active Virtual Priorities Register
Records active priorities for the Virtual Interrupt Domain.
AArch64 System register ICH_APR_EL2 bits [63:0] are architecturally mapped to AArch64 System register ICV_APR_EL1[63:0].
This register is present only when FEAT_GCIE is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented. Otherwise, direct accesses to ICH_APR_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
When FEAT_GCIE_LEGACY is implemented, AArch64 System register ICH_APR_EL2 bits [31:0] are architecturally mapped to AArch64 System register ICH_AP1R0_EL2[31:0].
ICH_APR_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| P31 | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Reserved, RES0.
Provides access to the active virtual priorities.
| P<x> | Meaning |
|---|---|
| 0b0 |
Priority not active |
| 0b1 |
Priority active |
This field is an alias of the equivalent field in ICV_APR_EL1.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICH_APR_EL2
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1000, op2 = 0b100)
if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then X{64}(t) = NVMem(0xB00); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICH_APR_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = ICH_APR_EL2(); end;
MSR ICH_APR_EL2, <Xt>
(op0 = 0b11, op1 = 0b100, CRn = 0b1100, CRm = 0b1000, op2 = 0b100)
if !(IsFeatureImplemented(FEAT_GCIE) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then NVMem(0xB00) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && (!IsFeatureImplemented(FEAT_GCIE_LEGACY) || (IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '0')) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then ICH_APR_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then ICH_APR_EL2() = X{64}(t); end;
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