ICC_PPI_ENABLER<n>_EL1 | Jon's Arm Reference

This register is present only when FEAT_GCIE is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_PPI_ENABLER<n>_EL1 are UNDEFINED.

Attributes

Field descriptions

EN<x>, bit [x], for x = 63 to 0:

PPI <(n * 64) + x> Enable.

EN<x>	Meaning
0b0	Disabled
0b1	Enabled

The reset behavior of this field is:

On a Warm reset, this field resets to an UNKNOWN value.

Accessing this field has the following behavior:

When !IsPPIImplemented((n * 64) + x), access to this field is RAZ/WI.
Access to this field is RAZ/WI if all the following are true:
- !IsPPIAssignedToCurrentDomain((n * 64) + x).
- PSTATE.EL IN {EL2, EL1}.
Otherwise, access to this field is RW.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICC_PPI_ENABLER<n>_EL1 ; Where n = 0-1

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1010, op2 = 0b11:n[0])

let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGRTR_EL2().ICC_PPI_ENABLERn_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_PPI_ENABLER_EL1(n); else X{64}(t) = ICC_PPI_ENABLER_EL1(n); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICC_PPI_ENABLER_EL1(n); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_PPI_ENABLER_EL1(n); end;

MSR ICC_PPI_ENABLER<n>_EL1, <Xt> ; Where n = 0-1

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1010, op2 = 0b11:n[0])

let n:integer = UInt(op2[0]); if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGWTR_EL2().ICC_PPI_ENABLERn_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_PPI_ENABLER_EL1(n) = X{64}(t); else ICC_PPI_ENABLER_EL1(n) = X{64}(t); end; elsif PSTATE.EL == EL2 then ICC_PPI_ENABLER_EL1(n) = X{64}(t); elsif PSTATE.EL == EL3 then ICC_PPI_ENABLER_EL1(n) = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EN63	EN62	EN61	EN60	EN59	EN58	EN57	EN56	EN55	EN54	EN53	EN52	EN51	EN50	EN49	EN48	EN47	EN46	EN45	EN44	EN43	EN42	EN41	EN40	EN39	EN38	EN37	EN36	EN35	EN34	EN33	EN32
EN31	EN30	EN29	EN28	EN27	EN26	EN25	EN24	EN23	EN22	EN21	EN20	EN19	EN18	EN17	EN16	EN15	EN14	EN13	EN12	EN11	EN10	EN9	EN8	EN7	EN6	EN5	EN4	EN3	EN2	EN1	EN0

ICC_PPI_ENABLER<n>_EL1, n = 0 - 1

Configuration

Attributes

Field descriptions

EN<x>, bit [x], for x = 63 to 0:

Access Instructions