Interrupt Controller Interrupt Priority Mask Register
Provides an interrupt priority filter. Only interrupts with a higher priority than the value in this register are signaled to the PE.
Writes to this register must be high performance and must ensure that no interrupt of lower priority than the written value occurs after the write, without requiring an ISB or an exception boundary.
AArch64 System register ICC_PMR_EL1 bits [31:0] are architecturally mapped to AArch32 System register ICC_PMR[31:0].
This register is present only when (GICv3 is implemented or FEAT_GCIE_LEGACY is implemented) and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_PMR_EL1 are UNDEFINED.
The effect of writes to ICC_PMR_EL1 are guaranteed to be visible to later instructions in the Execution stream. This ensures that no interrupts below the written PMR value will be taken after a write to this register is architecturally executed. For more information, see 'Observability of the effects of accesses to the GIC registers' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
ICC_PMR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | Priority | ||||||||||||||||||||||||||||||
Reserved, RES0.
The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.
The possible priority field values are as follows:
| Implemented priority bits | Possible priority field values | Number of priority levels |
|---|---|---|
| [7:0] | 0x00-0xFF (0-255), all values | 256 |
| [7:1] | 0x00-0xFE (0-254), even values only | 128 |
| [7:2] | 0x00-0xFC (0-252), in steps of 4 | 64 |
| [7:3] | 0x00-0xF8 (0-248), in steps of 8 | 32 |
| [7:4] | 0x00-0xF0 (0-240), in steps of 16 | 16 |
Unimplemented priority bits are RAZ/WI.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_PMR_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b0100, CRm = 0b0110, op2 = 0b000)
if !((IsFeatureImplemented(FEAT_GICv3) || IsFeatureImplemented(FEAT_GCIE_LEGACY)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) && (ICH_VCTLR_EL2().V3 == '0' || !EL2Enabled() || !(ICH_HCR_EL2().TC == '1' || HCR_EL2().FMO == '1' || HCR_EL2().IMO == '1')) then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then X{64}(t) = ICV_PMR_EL1(); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_PMR_EL1(); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ICC_PMR_EL1(); end; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ICC_PMR_EL1(); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) then Undefined(); elsif ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICC_PMR_EL1(); end; end;
MSR ICC_PMR_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b0100, CRm = 0b0110, op2 = 0b000)
if !((IsFeatureImplemented(FEAT_GICv3) || IsFeatureImplemented(FEAT_GCIE_LEGACY)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) && (ICH_VCTLR_EL2().V3 == '0' || !EL2Enabled() || !(ICH_HCR_EL2().TC == '1' || HCR_EL2().FMO == '1' || HCR_EL2().IMO == '1')) then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then ICV_PMR_EL1() = X{64}(t); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_PMR_EL1() = X{64}(t); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_PMR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_PMR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) then Undefined(); elsif ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICC_PMR_EL1() = X{64}(t); end; end;
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