Interrupt Controller Interrupt Priority Control Register (EL3)
Controls the Physical priority mask for the physical CPU interface for the EL3 Interrupt Domain.
This register is present only when FEAT_GCIE is implemented, EL3 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_PCR_EL3 are UNDEFINED.
ICC_PCR_EL3 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | PRIORITY | ||||||||||||||||||||||||||||||
Reserved, RES0.
The priority mask for the EL3 Interrupt Domain.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_PCR_EL3
(op0 = 0b11, op1 = 0b110, CRn = 0b1100, CRm = 0b1000, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_GCIE) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_PCR_EL3(); end;
MSR ICC_PCR_EL3, <Xt>
(op0 = 0b11, op1 = 0b110, CRn = 0b1100, CRm = 0b1000, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_GCIE) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then ICC_PCR_EL3() = X{64}(t); end;
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