Interrupt Controller ID Register 0
Contains information about features implemented by the GICv5 CPU interface.
This register is present only when FEAT_GCIE is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_IDR0_EL1 are UNDEFINED.
ICC_IDR0_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | GCIE_LEGACY | PRI_BITS | ID_BITS | ||||||||||||||||||||||||||||
Reserved, RES0.
Indicates support for legacy GICv3.3 virtual CPU interface.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| GCIE_LEGACY | Meaning |
|---|---|
| 0b0000 |
Legacy GICv3.3 virtual CPU interface is not implemented |
| 0b0001 |
Legacy GICv3.3 virtual CPU interface is implemented |
FEAT_GCIE_LEGACY extension implements the functionality identified by the value 0b0001.
Access to this field is RO.
The number of priority bits implemented, minus one.
The number of supported priority bits is 5.
Other values are reserved.
Reads as 0b0100.
Access to this field is RO.
Identifier bits.
The number of interrupt identifier bits supported.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| ID_BITS | Meaning |
|---|---|
| 0b0000 |
16 bits |
| 0b0001 |
24 bits |
Access to this field is RO.
This register is Read-only.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_IDR0_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1010, op2 = 0b010)
if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGRTR_EL2().ICC_IDRn_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = ICC_IDR0_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICC_IDR0_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_IDR0_EL1(); end;
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