Interrupt Controller Interrupt Configuration and State Register
Reports the configuration and state of the INTID specified to a previous GIC request interrupt configuration instruction.
This register is present only when FEAT_GCIE is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_ICSR_EL1 are UNDEFINED.
ICC_ICSR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | IAFFID | ||||||||||||||||||||||||||||||
| RES0 | Priority | RES0 | HM | Active | IRM | Pending | Enabled | F | |||||||||||||||||||||||
Reserved, RES0.
The interrupt Affinity value.
The IRS may support fewer than 16 bits of IAFFID. Upper bits not implemented by the IRS are returned as zero.
When IRM is 1, this field is IMPLEMENTATION DEFINED.
The reset behavior of this field is:
Reserved, RES0.
The priority of the interrupt.
The reset behavior of this field is:
Reserved, RES0.
The Handling mode of the interrupt.
| HM | Meaning |
|---|---|
| 0b0 |
Edge |
| 0b1 |
Level |
The reset behavior of this field is:
The interrupt Active state.
| Active | Meaning |
|---|---|
| 0b0 |
Inactive |
| 0b1 |
Active |
The reset behavior of this field is:
Interrupt Routing mode.
| IRM | Meaning |
|---|---|
| 0b0 |
Targeted. |
| 0b1 |
1ofN. |
The reset behavior of this field is:
The interrupt Pending state.
| Pending | Meaning |
|---|---|
| 0b0 |
Not pending |
| 0b1 |
Pending |
The reset behavior of this field is:
The interrupt individual enable.
| Enabled | Meaning |
|---|---|
| 0b0 |
Disabled |
| 0b1 |
Enabled |
The reset behavior of this field is:
Indicates whether the IRS returned valid data.
| F | Meaning |
|---|---|
| 0b0 |
Request completed successfully. |
| 0b1 |
Request did not complete successfully. |
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_ICSR_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1010, op2 = 0b100)
if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGRTR_EL2().ICC_ICSR_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = ICC_ICSR_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICC_ICSR_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_ICSR_EL1(); end;
MSR ICC_ICSR_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1010, op2 = 0b100)
if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGWTR_EL2().ICC_ICSR_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else ICC_ICSR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then ICC_ICSR_EL1() = X{64}(t); elsif PSTATE.EL == EL3 then ICC_ICSR_EL1() = X{64}(t); end;
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