Interrupt Controller Interrupt Acknowledge Register 0
The PE reads this register to obtain the INTID of the signaled Group 0 interrupt. This read acts as an acknowledge for the interrupt.
AArch64 System register ICC_IAR0_EL1 bits [31:0] performs the same function as AArch32 System register ICC_IAR0[31:0].
This register is present only when (GICv3 is implemented or FEAT_GCIE_LEGACY is implemented) and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_IAR0_EL1 are UNDEFINED.
When FIQs are masked by the PE, the side-effects of direct reads of ICC_IAR0_EL1 that updates the Running priority and affect signaling of an interrupt exception are guaranteed to be visible to later instructions in the Execution stream. For information on PE interrupt masking see Arm® Architecture Reference Manual for A-profile architecture. This ensures that the effect of activating an interrupt on the signaling of interrupt exceptions is observed when a read of this register is architecturally executed so that no spurious interrupt exception occurs if interrupts are unmasked by an instruction immediately following the read. For more information, see 'Observability of the effects of accesses to the GIC registers'.
ICC_IAR0_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | INTID | ||||||||||||||||||||||||||||||
Reserved, RES0.
The INTID of the signaled interrupt.
This is the INTID of the highest priority pending interrupt, if that interrupt is of sufficient priority for it to be signaled to the PE, and if it can be acknowledged at the current Security state and Exception level.
If the highest priority pending interrupt is not observable, this field contains a special INTID to indicate the reason. For more information, see 'Special INTIDs' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR_EL1.IDbits and ICC_CTLR_EL3.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_IAR0_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1000, op2 = 0b000)
if !((IsFeatureImplemented(FEAT_GICv3) || IsFeatureImplemented(FEAT_GCIE_LEGACY)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().FIQ == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) && (ICH_VCTLR_EL2().V3 == '0' || !EL2Enabled() || !(ICH_HCR_EL2().TALL0 == '1' || HCR_EL2().FMO == '1')) then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TALL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then X{64}(t) = ICV_IAR0_EL1(); elsif HaveEL(EL3) && SCR_EL3().FIQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ICC_IAR0_EL1(); end; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().FIQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ICC_IAR0_EL1(); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) then Undefined(); elsif ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICC_IAR0_EL1(); end; end;
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