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ICC_HPPIR_EL3

Interrupt Controller Physical Highest Priority Pending Interrupt Register (EL3)

Reports the HPPI for the EL3 Interrupt Domain.

Configuration

This register is present only when FEAT_GCIE is implemented, EL3 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_HPPIR_EL3 are UNDEFINED.

Attributes

ICC_HPPIR_EL3 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0HPPIV
TYPERES0ID

Bits [63:33]:

Reserved, RES0.

HPPIV, bit [32]:

HPPI valid.

There is an HPPI with Sufficient priority for the Interrupt Domain.

HPPIVMeaning
0b0

Invalid: There is no HPPI with Sufficient priority for the Interrupt Domain.

0b1

VALID: There is an HPPI with Sufficient priority for the Interrupt Domain.

If ICC_HPPIR_EL3.HPPIV is 1, ID and TYPE together form the INTID of the HPPI for the Interrupt Domain.

TYPE, bits [31:29]:

The encoding of this field depends on the value of HPPIV as described below:

TYPEMeaning
0b001

PPI

0b010

LPI

0b011

SPI

Values not defined above are reserved.

Bits [28:24]:

Reserved, RES0.

ID, bits [23:0]:

The encoding of this field depends on the value of HPPIV as described below:

Access Instructions

This register is Read-only.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICC_HPPIR_EL3

(op0 = 0b11, op1 = 0b110, CRn = 0b1100, CRm = 0b1001, op2 = 0b001)

if !(IsFeatureImplemented(FEAT_GCIE) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_HPPIR_EL3(); end;


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