Interrupt Controller Physical Highest Priority Pending Interrupt Register (EL1)
Reports the HPPI for the Physical Interrupt Domain associated with the Security state selected by SCR_EL3.{NS, NSE}.
This register is present only when FEAT_GCIE is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_HPPIR_EL1 are UNDEFINED.
ICC_HPPIR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | HPPIV | ||||||||||||||||||||||||||||||
| TYPE | RES0 | ID | |||||||||||||||||||||||||||||
Reserved, RES0.
HPPI valid.
There is an HPPI with Sufficient priority for the Interrupt Domain.
| HPPIV | Meaning |
|---|---|
| 0b0 |
Invalid: There is no HPPI with Sufficient priority for the Interrupt Domain. |
| 0b1 |
VALID: There is an HPPI with Sufficient priority for the Interrupt Domain. |
If ICC_HPPIR_EL1.HPPIV is 1, ID and TYPE together form the INTID of the HPPI for the Interrupt Domain.
The encoding of this field depends on the value of HPPIV as described below:
If ICC_HPPIR_EL1.HPPIV is 0, TYPE is RES0.
If ICC_HPPIR_EL1.HPPIV is 1, TYPE specifies the Type of the interrupt.
| TYPE | Meaning |
|---|---|
| 0b001 |
PPI |
| 0b010 |
LPI |
| 0b011 |
SPI |
Values not defined above are reserved.
Reserved, RES0.
The encoding of this field depends on the value of HPPIV as described below:
If ICC_HPPIR_EL1.HPPIV is 0, ID is RES0.
If ICC_HPPIR_EL1.HPPIV is 1, ID specifies the interrupt ID.
This register is Read-only.
When accessed at EL3, if SCR_EL3.{NS, NSE} select a reserved value, the behavior is CONSTRAINED UNPREDICTABLE with the permitted options:
SCR_EL3.{NS, NSE} is treated as having an UNKNOWN value.
The access is treated as a NOP.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_HPPIR_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1010, op2 = 0b011)
if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGRTR_EL2().ICC_HPPIR_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_HPPIR_EL1(); else X{64}(t) = ICC_HPPIR_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ICC_HPPIR_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_HPPIR_EL1(); end;
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