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ICC_DIR_EL1

Interrupt Controller Deactivate Interrupt Register

When interrupt priority drop is separated from interrupt deactivation, a write to this register deactivates the specified interrupt.

Configuration

AArch64 System register ICC_DIR_EL1 bits [31:0] performs the same function as AArch32 System register ICC_DIR[31:0].

This register is present only when (GICv3 is implemented or FEAT_GCIE_LEGACY is implemented) and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_DIR_EL1 are UNDEFINED.

Attributes

ICC_DIR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0INTID

Bits [63:24]:

Reserved, RES0.

INTID, bits [23:0]:

The INTID of the interrupt to be deactivated.

This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR_EL1.IDbits and ICC_CTLR_EL3.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.

Access Instructions

There are two cases when writing to ICC_DIR_EL1 that were UNPREDICTABLE for a corresponding GICv2 write to GICC_DIR:

Accesses to this register use the following encodings in the System register encoding space:

MSR ICC_DIR_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b1100, CRm = 0b1011, op2 = 0b001)

if !((IsFeatureImplemented(FEAT_GICv3) || IsFeatureImplemented(FEAT_GCIE_LEGACY)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) && (ICH_VCTLR_EL2().V3 == '0' || !EL2Enabled() || !(ICH_HCR_EL2().TDIR == '1' || ICH_HCR_EL2().TC == '1' || HCR_EL2().FMO == '1' || HCR_EL2().IMO == '1')) then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TDIR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then ICV_DIR_EL1() = X{64}(t); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_DIR_EL1() = X{64}(t); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_DIR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_DIR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_GCIE_LEGACY) then Undefined(); elsif ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICC_DIR_EL1() = X{64}(t); end; end;


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