Interrupt Controller Physical Control Register (EL3)
Controls behavior of the CPU interface in the EL3 Interrupt Domain.
AArch64 System register ICC_CR0_EL3 bits [2:1] are architecturally mapped to AArch64 System register ICC_CR0_EL1[2:1].
This register is present only when FEAT_GCIE is implemented, EL3 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_CR0_EL3 are UNDEFINED.
ICC_CR0_EL3 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | PID | ||||||||||||||||||||||||||||||
| RES0 | LINK_IDLE | LINK | EN | ||||||||||||||||||||||||||||
Reserved, RES0.
Preemptive Interrupt Domain.
The PE behaves as if there is no Preemptive Interrupt Domain when any of the following are true:
This field is set to 0b10.
This field is set to an Interrupt Domain that is not implemented.
| PID | Meaning |
|---|---|
| 0b00 |
Secure Interrupt Domain |
| 0b01 |
Non-secure Interrupt Domain |
| 0b10 |
None |
| 0b11 |
Realm Interrupt Domain |
The reset behavior of this field is:
Reserved, RES0.
Whether the link between the CPU interface and the IRI is in the process of connecting or disconnecting.
| LINK_IDLE | Meaning |
|---|---|
| 0b0 |
The link between the CPU interface and the IRI is in the process of connecting or disconnecting. |
| 0b1 |
The link between the CPU interface and the IRI is not in the process of connecting or disconnecting. |
When this field is 0, if the system has been properly configured and a connection can be made between the CPU interface and the IRI, the field will become 1 in finite time. If the system has not been properly configured and an attempt to connect the CPU interface to the IRI is made, this field may remain 0 indefinitely.
In an implementation where the CPU interface is always connected to the IRI, this field is permitted to be implemented as RAO/WI.
The reset behavior of this field is:
Access to this field is RO.
Whether the link between the CPU interface and the IRI is connected.
| LINK | Meaning |
|---|---|
| 0b0 |
The link between the CPU interface and the IRI is disconnected. |
| 0b1 |
The link between the CPU interface and the IRI is connected. |
On a read, all of the following are true:
On a write, all of the following are true:
In an implementation where the CPU interface is always connected to the IRI, this field is permitted to be implemented as RAO/WI.
The reset behavior of this field is:
Accessing this field has the following behavior:
Enable interrupts for the EL3 Interrupt Domain.
When this field is set to 0, the PE behaves as if there is no HPPI of Sufficient priority in the EL3 Interrupt Domain.
| EN | Meaning |
|---|---|
| 0b0 |
Disabled. |
| 0b1 |
Enabled. |
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_CR0_EL3
(op0 = 0b11, op1 = 0b110, CRn = 0b1100, CRm = 0b1001, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_GCIE) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_CR0_EL3(); end;
MSR ICC_CR0_EL3, <Xt>
(op0 = 0b11, op1 = 0b110, CRn = 0b1100, CRm = 0b1001, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_GCIE) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then ICC_CR0_EL3() = X{64}(t); end;
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