Interrupt Controller Physical Control Register (EL1)
Controls behavior of the physical CPU interface for the Non-secure, Realm, and Secure Interrupt Domains.
This register is banked between ICC_CR0_EL1 and ICC_CR0_EL1_NS and ICC_CR0_EL1_RL and ICC_CR0_EL1_S.
AArch64 System register ICC_CR0_EL1 bits [2:1] are architecturally mapped to AArch64 System register ICC_CR0_EL3[2:1] when EL3 is implemented.
This register is present only when FEAT_GCIE is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_CR0_EL1 are UNDEFINED.
Direct accesses at EL3 use the register copy selected based on the following:
When the Effective value of SCR_EL3.NS is 0, direct accesses use the Secure banked copy.
When the Effective value of SCR_EL3.{NS,NSE} is {1,1}, direct accesses use the Realm banked copy.
Otherwise, direct accesses use the Non-secure banked copy.
ICC_CR0_EL1 is a 64-bit register.
This register has the following instances:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | PID | IPPT | |||||||||||||||||||||||||||||
| RES0 | LINK_IDLE | LINK | EN | ||||||||||||||||||||||||||||
Reserved, RES0.
Preemptive Interrupt Domain. Indicates whether the Interrupt Domain associated with the Security state selected by SCR_EL3.{NSE,NS} is the Preemptive Interrupt Domain.
Access to this field is RO.
Reserved, RAZ/WI.
Interrupt Preemptive Priority Threshold value for the Preemptive Interrupt Domain.
ICC_CR0_EL1.IPPT is a 6 bits field to ensure it can be strictly higher than the interrupt priority, which is a 5-bit unsigned value.
See 'Preemptive interrupts' in Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 5 (ARM IHI 111701) for more information.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Whether the link between the CPU interface and the IRI is in the process of connecting or disconnecting.
| LINK_IDLE | Meaning |
|---|---|
| 0b0 |
The link between the CPU interface and the IRI is in the process of connecting or disconnecting. |
| 0b1 |
The link between the CPU interface and the IRI is not in the process of connecting or disconnecting. |
When this field is 0, if the system has been properly configured and a connection can be made between the CPU interface and the IRI, the field will become 1 in finite time. If the system has not been properly configured and an attempt to connect the CPU interface to the IRI is made, this field may remain 0 indefinitely.
In an implementation where the CPU interface is always connected to the IRI, this field is permitted to be implemented as RAO/WI.
The reset behavior of this field is:
Access to this field is RO.
Whether the link between the CPU interface and the IRI is connected.
| LINK | Meaning |
|---|---|
| 0b0 |
The link between the CPU interface and the IRI is disconnected. |
| 0b1 |
The link between the CPU interface and the IRI is connected. |
On a read, all of the following are true:
On a write, all of the following are true:
In an implementation where the CPU interface is always connected to the IRI, this field is permitted to be implemented as RAO/WI.
The reset behavior of this field is:
Accessing this field has the following behavior:
Enable interrupts for the Interrupt Domain.
When this field is 0, there is no HPPI of Sufficient priority for the Interrupt Domain.
| EN | Meaning |
|---|---|
| 0b0 |
Disabled. |
| 0b1 |
Enabled. |
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_CR0_EL1
(op0 = 0b11, op1 = 0b001, CRn = 0b1100, CRm = 0b0000, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGRTR_EL2().ICC_CR0_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_CR0_EL1(); elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CR0_EL1_S(); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_RL(); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_NS(); else Undefined(); end; else X{64}(t) = ICC_CR0_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CR0_EL1_S(); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_RL(); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_NS(); else Undefined(); end; else X{64}(t) = ICC_CR0_EL1(); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CR0_EL1_S(); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_RL(); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_CR0_EL1_NS(); else Undefined(); end; end;
MSR ICC_CR0_EL1, <Xt>
(op0 = 0b11, op1 = 0b001, CRn = 0b1100, CRm = 0b0000, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGWTR_EL2().ICC_CR0_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_CR0_EL1() = X{64}(t); elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_CR0_EL1_S() = X{64}(t); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_RL() = X{64}(t); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_NS() = X{64}(t); else Undefined(); end; else ICC_CR0_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_CR0_EL1_S() = X{64}(t); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_RL() = X{64}(t); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_NS() = X{64}(t); else Undefined(); end; else ICC_CR0_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then ICC_CR0_EL1_S() = X{64}(t); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_RL() = X{64}(t); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then ICC_CR0_EL1_NS() = X{64}(t); else Undefined(); end; end;
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