Interrupt Controller Physical Active Priorities Register for EL3
Records active priorities for the EL3 Interrupt Domain.
This register is present only when FEAT_GCIE is implemented, EL3 is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_APR_EL3 are UNDEFINED.
ICC_APR_EL3 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| P31 | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Reserved, RES0.
Provides access to the active priorities.
| P<x> | Meaning |
|---|---|
| 0b0 |
Priority not active |
| 0b1 |
Priority active |
Fields in this register are indexed using the 5-bit priority as an unsigned integer, P[Priority].
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_APR_EL3
(op0 = 0b11, op1 = 0b110, CRn = 0b1100, CRm = 0b1000, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_GCIE) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_APR_EL3(); end;
MSR ICC_APR_EL3, <Xt>
(op0 = 0b11, op1 = 0b110, CRn = 0b1100, CRm = 0b1000, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_GCIE) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then ICC_APR_EL3() = X{64}(t); end;
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