Interrupt Controller Physical Active Priorities Register (EL1)
Records physical active priorities for the Non-secure, Realm, and Secure Interrupt Domains.
This register is banked between ICC_APR_EL1 and ICC_APR_EL1_NS and ICC_APR_EL1_RL and ICC_APR_EL1_S.
This register is present only when FEAT_GCIE is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to ICC_APR_EL1 are UNDEFINED.
Direct accesses at EL3 use the register copy selected based on the following:
When the Effective value of SCR_EL3.NS is 0, direct accesses use the Secure banked copy.
When the Effective value of SCR_EL3.{NS,NSE} is {1,1}, direct accesses use the Realm banked copy.
Otherwise, direct accesses use the Non-secure banked copy.
ICC_APR_EL1 is a 64-bit register.
This register has the following instances:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| P31 | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Reserved, RES0.
Provides access to the active priorities.
| P<x> | Meaning |
|---|---|
| 0b0 |
Priority not active |
| 0b1 |
Priority active |
Fields in this register are indexed using the 5-bit priority as an unsigned integer, P[Priority].
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ICC_APR_EL1
(op0 = 0b11, op1 = 0b001, CRn = 0b1100, CRm = 0b0000, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGRTR_EL2().ICC_APR_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_APR_EL1(); elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_APR_EL1_S(); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_APR_EL1_RL(); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_APR_EL1_NS(); else Undefined(); end; else X{64}(t) = ICC_APR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_APR_EL1_S(); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_APR_EL1_RL(); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_APR_EL1_NS(); else Undefined(); end; else X{64}(t) = ICC_APR_EL1(); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_APR_EL1_S(); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_APR_EL1_RL(); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then X{64}(t) = ICC_APR_EL1_NS(); else Undefined(); end; end;
MSR ICC_APR_EL1, <Xt>
(op0 = 0b11, op1 = 0b001, CRn = 0b1100, CRm = 0b0000, op2 = 0b000)
if !(IsFeatureImplemented(FEAT_GCIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().IMO == '1' && IsFeatureImplemented(FEAT_GCIE_LEGACY) && ICH_VCTLR_EL2().V3 == '1' then Undefined(); elsif EL2Enabled() && ICH_HFGWTR_EL2().ICC_APR_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_APR_EL1() = X{64}(t); elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_APR_EL1_S() = X{64}(t); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then ICC_APR_EL1_RL() = X{64}(t); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then ICC_APR_EL1_NS() = X{64}(t); else Undefined(); end; else ICC_APR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_APR_EL1_S() = X{64}(t); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then ICC_APR_EL1_RL() = X{64}(t); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then ICC_APR_EL1_NS() = X{64}(t); else Undefined(); end; else ICC_APR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then ICC_APR_EL1_S() = X{64}(t); elsif IsFeatureImplemented(FEAT_RME) && EffectiveSCR_EL3_NSE() == '1' && EffectiveSCR_EL3_NS() == '1' then ICC_APR_EL1_RL() = X{64}(t); elsif (!IsFeatureImplemented(FEAT_RME) || EffectiveSCR_EL3_NSE() == '0') && EffectiveSCR_EL3_NS() == '1' then ICC_APR_EL1_NS() = X{64}(t); else Undefined(); end; end;
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