HCRMASK_EL2

This register is present only when FEAT_SRMASK2 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to HCRMASK_EL2 are UNDEFINED.

Attributes

Field descriptions

Bits [63:61]:

TWEDEL, bit [60] when FEAT_TWED is implemented:

Mask bit for TWEDEL.

TWEDEL	Meaning
0b0	HCR_EL2.TWEDEL is writable.
0b1	HCR_EL2.TWEDEL is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TWEDEn, bit [59] when FEAT_TWED is implemented:

Mask bit for TWEDEn.

TWEDEn	Meaning
0b0	HCR_EL2.TWEDEn is writable.
0b1	HCR_EL2.TWEDEn is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TID5, bit [58] when FEAT_MTE2 is implemented:

Mask bit for TID5.

TID5	Meaning
0b0	HCR_EL2.TID5 is writable.
0b1	HCR_EL2.TID5 is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

DCT, bit [57] when FEAT_MTE2 is implemented:

Mask bit for DCT.

DCT	Meaning
0b0	HCR_EL2.DCT is writable.
0b1	HCR_EL2.DCT is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

ATA, bit [56] when FEAT_MTE2 is implemented:

Mask bit for ATA.

ATA	Meaning
0b0	HCR_EL2.ATA is writable.
0b1	HCR_EL2.ATA is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TTLBOS, bit [55] when FEAT_EVT2 is implemented:

Mask bit for TTLBOS.

TTLBOS	Meaning
0b0	HCR_EL2.TTLBOS is writable.
0b1	HCR_EL2.TTLBOS is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TTLBIS, bit [54] when FEAT_EVT2 is implemented:

Mask bit for TTLBIS.

TTLBIS	Meaning
0b0	HCR_EL2.TTLBIS is writable.
0b1	HCR_EL2.TTLBIS is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

EnSCXT, bit [53] when FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented:

Mask bit for EnSCXT.

EnSCXT	Meaning
0b0	HCR_EL2.EnSCXT is writable.
0b1	HCR_EL2.EnSCXT is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TOCU, bit [52] when FEAT_EVT is implemented:

Mask bit for TOCU.

TOCU	Meaning
0b0	HCR_EL2.TOCU is writable.
0b1	HCR_EL2.TOCU is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

AMVOFFEN, bit [51] when FEAT_AMUv1p1 is implemented:

Mask bit for AMVOFFEN.

AMVOFFEN	Meaning
0b0	HCR_EL2.AMVOFFEN is writable.
0b1	HCR_EL2.AMVOFFEN is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TICAB, bit [50] when FEAT_EVT is implemented:

Mask bit for TICAB.

TICAB	Meaning
0b0	HCR_EL2.TICAB is writable.
0b1	HCR_EL2.TICAB is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TID4, bit [49] when FEAT_EVT is implemented:

Mask bit for TID4.

TID4	Meaning
0b0	HCR_EL2.TID4 is writable.
0b1	HCR_EL2.TID4 is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

GPF, bit [48] when FEAT_RME is implemented:

Mask bit for GPF.

GPF	Meaning
0b0	HCR_EL2.GPF is writable.
0b1	HCR_EL2.GPF is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

FIEN, bit [47] when FEAT_RASv1p1 is implemented:

Mask bit for FIEN.

FIEN	Meaning
0b0	HCR_EL2.FIEN is writable.
0b1	HCR_EL2.FIEN is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

FWB, bit [46] when FEAT_S2FWB is implemented:

Mask bit for FWB.

FWB	Meaning
0b0	HCR_EL2.FWB is writable.
0b1	HCR_EL2.FWB is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

NV2, bit [45] when FEAT_NV2 is implemented:

Mask bit for NV2.

NV2	Meaning
0b0	HCR_EL2.NV2 is writable.
0b1	HCR_EL2.NV2 is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

AT, bit [44] when FEAT_NV is implemented:

Mask bit for AT.

AT	Meaning
0b0	HCR_EL2.AT is writable.
0b1	HCR_EL2.AT is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

NV1, bit [43] when FEAT_NV is implemented:

Mask bit for NV1.

NV1	Meaning
0b0	HCR_EL2.NV1 is writable.
0b1	HCR_EL2.NV1 is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

NV, bit [42] when FEAT_NV is implemented:

Mask bit for NV.

NV	Meaning
0b0	HCR_EL2.NV is writable.
0b1	HCR_EL2.NV is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

API, bit [41] when FEAT_PAuth is implemented:

Mask bit for API.

API	Meaning
0b0	HCR_EL2.API is writable.
0b1	HCR_EL2.API is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

APK, bit [40] when FEAT_PAuth is implemented:

Mask bit for APK.

APK	Meaning
0b0	HCR_EL2.APK is writable.
0b1	HCR_EL2.APK is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [39:38]:

TEA, bit [37] when FEAT_RAS is implemented:

Mask bit for TEA.

TEA	Meaning
0b0	HCR_EL2.TEA is writable.
0b1	HCR_EL2.TEA is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TERR, bit [36] when FEAT_RAS is implemented:

Mask bit for TERR.

TERR	Meaning
0b0	HCR_EL2.TERR is writable.
0b1	HCR_EL2.TERR is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TLOR, bit [35] when FEAT_LOR is implemented:

Mask bit for TLOR.

TLOR	Meaning
0b0	HCR_EL2.TLOR is writable.
0b1	HCR_EL2.TLOR is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

E2H, bit [34] when FEAT_VHE is implemented and FEAT_E2H0 is implemented:

Mask bit for E2H.

E2H	Meaning
0b0	HCR_EL2.E2H is writable.
0b1	HCR_EL2.E2H is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

ID, bit [33]:

Mask bit for ID.

ID	Meaning
0b0	HCR_EL2.ID is writable.
0b1	HCR_EL2.ID is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

CD, bit [32]:

Mask bit for CD.

CD	Meaning
0b0	HCR_EL2.CD is writable.
0b1	HCR_EL2.CD is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

RW, bit [31] when FEAT_AA32EL1 is implemented:

Mask bit for RW.

RW	Meaning
0b0	HCR_EL2.RW is writable.
0b1	HCR_EL2.RW is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TRVM, bit [30]:

Mask bit for TRVM.

TRVM	Meaning
0b0	HCR_EL2.TRVM is writable.
0b1	HCR_EL2.TRVM is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

HCD, bit [29] when EL3 is not implemented:

Mask bit for HCD.

HCD	Meaning
0b0	HCR_EL2.HCD is writable.
0b1	HCR_EL2.HCD is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TDZ, bit [28]:

Mask bit for TDZ.

TDZ	Meaning
0b0	HCR_EL2.TDZ is writable.
0b1	HCR_EL2.TDZ is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TGE, bit [27]:

Mask bit for TGE.

TGE	Meaning
0b0	HCR_EL2.TGE is writable.
0b1	HCR_EL2.TGE is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TVM, bit [26]:

Mask bit for TVM.

TVM	Meaning
0b0	HCR_EL2.TVM is writable.
0b1	HCR_EL2.TVM is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TTLB, bit [25]:

Mask bit for TTLB.

TTLB	Meaning
0b0	HCR_EL2.TTLB is writable.
0b1	HCR_EL2.TTLB is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TPU, bit [24]:

Mask bit for TPU.

TPU	Meaning
0b0	HCR_EL2.TPU is writable.
0b1	HCR_EL2.TPU is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TPCP, bit [23]:

Mask bit for TPCP.

TPCP	Meaning
0b0	HCR_EL2.TPCP is writable.
0b1	HCR_EL2.TPCP is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TSW, bit [22]:

Mask bit for TSW.

TSW	Meaning
0b0	HCR_EL2.TSW is writable.
0b1	HCR_EL2.TSW is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TACR, bit [21]:

Mask bit for TACR.

TACR	Meaning
0b0	HCR_EL2.TACR is writable.
0b1	HCR_EL2.TACR is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TIDCP, bit [20]:

Mask bit for TIDCP.

TIDCP	Meaning
0b0	HCR_EL2.TIDCP is writable.
0b1	HCR_EL2.TIDCP is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TSC, bit [19]:

Mask bit for TSC.

TSC	Meaning
0b0	HCR_EL2.TSC is writable.
0b1	HCR_EL2.TSC is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TID3, bit [18]:

Mask bit for TID3.

TID3	Meaning
0b0	HCR_EL2.TID3 is writable.
0b1	HCR_EL2.TID3 is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TID2, bit [17]:

Mask bit for TID2.

TID2	Meaning
0b0	HCR_EL2.TID2 is writable.
0b1	HCR_EL2.TID2 is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TID1, bit [16]:

Mask bit for TID1.

TID1	Meaning
0b0	HCR_EL2.TID1 is writable.
0b1	HCR_EL2.TID1 is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TID0, bit [15] when FEAT_AA32 is implemented:

Mask bit for TID0.

TID0	Meaning
0b0	HCR_EL2.TID0 is writable.
0b1	HCR_EL2.TID0 is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

TWE, bit [14]:

Mask bit for TWE.

TWE	Meaning
0b0	HCR_EL2.TWE is writable.
0b1	HCR_EL2.TWE is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

TWI, bit [13]:

Mask bit for TWI.

TWI	Meaning
0b0	HCR_EL2.TWI is writable.
0b1	HCR_EL2.TWI is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

DC, bit [12]:

Mask bit for DC.

DC	Meaning
0b0	HCR_EL2.DC is writable.
0b1	HCR_EL2.DC is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Bit [11]:

BSU, bit [10]:

Mask bit for BSU.

BSU	Meaning
0b0	HCR_EL2.BSU is writable.
0b1	HCR_EL2.BSU is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

FB, bit [9]:

Mask bit for FB.

FB	Meaning
0b0	HCR_EL2.FB is writable.
0b1	HCR_EL2.FB is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

VSE, bit [8]:

Mask bit for VSE.

VSE	Meaning
0b0	HCR_EL2.VSE is writable.
0b1	HCR_EL2.VSE is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

VI, bit [7]:

Mask bit for VI.

VI	Meaning
0b0	HCR_EL2.VI is writable.
0b1	HCR_EL2.VI is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

VF, bit [6]:

Mask bit for VF.

VF	Meaning
0b0	HCR_EL2.VF is writable.
0b1	HCR_EL2.VF is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

AMO, bit [5]:

Mask bit for AMO.

AMO	Meaning
0b0	HCR_EL2.AMO is writable.
0b1	HCR_EL2.AMO is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

IMO, bit [4]:

Mask bit for IMO.

IMO	Meaning
0b0	HCR_EL2.IMO is writable.
0b1	HCR_EL2.IMO is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

FMO, bit [3]:

Mask bit for FMO.

FMO	Meaning
0b0	HCR_EL2.FMO is writable.
0b1	HCR_EL2.FMO is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

PTW, bit [2]:

Mask bit for PTW.

PTW	Meaning
0b0	HCR_EL2.PTW is writable.
0b1	HCR_EL2.PTW is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

SWIO, bit [1]:

Mask bit for SWIO.

SWIO	Meaning
0b0	HCR_EL2.SWIO is writable.
0b1	HCR_EL2.SWIO is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

VM, bit [0]:

Mask bit for VM.

VM	Meaning
0b0	HCR_EL2.VM is writable.
0b1	HCR_EL2.VM is not writable.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HCRMASK_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0101, op2 = 0b110)

if !(IsFeatureImplemented(FEAT_SRMASK2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR2_EL3().SRMASK2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCRX_EL2_NVTGE() == '1' && (!HaveEL(EL3) || SCR2_EL3().SRMASK2En == '1') then X{64}(t) = NVHCRMASK_EL2(); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_SCR2) && SCR2_EL3().SRMASK2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HCRMASK_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HCRMASK_EL2(); end;

MSR HCRMASK_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0101, op2 = 0b110)

if !(IsFeatureImplemented(FEAT_SRMASK2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR2_EL3().SRMASK2En == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCRX_EL2_NVTGE() == '1' && (!HaveEL(EL3) || SCR2_EL3().SRMASK2En == '1') then if !IsZero(NVHCRMASK_EL2()) then Undefined(); else NVHCRMASK_EL2() = X{64}(t); end; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_SCR2) && SCR2_EL3().SRMASK2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsZero(HCRMASK_EL2()) then Undefined(); else HCRMASK_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HCRMASK_EL2() = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0			TWEDEL	TWEDEn	TID5	DCT	ATA	TTLBOS	TTLBIS	EnSCXT	TOCU	AMVOFFEN	TICAB	TID4	GPF	FIEN	FWB	NV2	AT	NV1	NV	API	APK	RES0		TEA	TERR	TLOR	E2H	ID	CD
RW	TRVM	HCD	TDZ	TGE	TVM	TTLB	TPU	TPCP	TSW	TACR	TIDCP	TSC	TID3	TID2	TID1	TID0	TWE	TWI	DC	RES0	BSU	FB	VSE	VI	VF	AMO	IMO	FMO	PTW	SWIO	VM

Configuration

Attributes

Field descriptions

Bits [63:61]:

TWEDEL, bit [60] when FEAT_TWED is implemented:

Otherwise:

TWEDEn, bit [59] when FEAT_TWED is implemented:

Otherwise:

TID5, bit [58] when FEAT_MTE2 is implemented:

Otherwise:

DCT, bit [57] when FEAT_MTE2 is implemented:

Otherwise:

ATA, bit [56] when FEAT_MTE2 is implemented:

Otherwise:

TTLBOS, bit [55] when FEAT_EVT2 is implemented:

Otherwise:

TTLBIS, bit [54] when FEAT_EVT2 is implemented:

Otherwise:

EnSCXT, bit [53] when FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented:

Otherwise:

TOCU, bit [52] when FEAT_EVT is implemented:

Otherwise:

AMVOFFEN, bit [51] when FEAT_AMUv1p1 is implemented:

Otherwise:

TICAB, bit [50] when FEAT_EVT is implemented:

Otherwise:

TID4, bit [49] when FEAT_EVT is implemented:

Otherwise:

GPF, bit [48] when FEAT_RME is implemented:

Otherwise:

FIEN, bit [47] when FEAT_RASv1p1 is implemented:

Otherwise:

FWB, bit [46] when FEAT_S2FWB is implemented:

Otherwise:

NV2, bit [45] when FEAT_NV2 is implemented:

Otherwise:

AT, bit [44] when FEAT_NV is implemented:

Otherwise:

NV1, bit [43] when FEAT_NV is implemented:

Otherwise:

NV, bit [42] when FEAT_NV is implemented:

Otherwise:

API, bit [41] when FEAT_PAuth is implemented:

Otherwise:

APK, bit [40] when FEAT_PAuth is implemented:

Otherwise:

Bits [39:38]:

TEA, bit [37] when FEAT_RAS is implemented:

Otherwise:

TERR, bit [36] when FEAT_RAS is implemented:

Otherwise:

TLOR, bit [35] when FEAT_LOR is implemented:

Otherwise:

E2H, bit [34] when FEAT_VHE is implemented and FEAT_E2H0 is implemented:

Otherwise:

ID, bit [33]:

CD, bit [32]:

RW, bit [31] when FEAT_AA32EL1 is implemented:

Otherwise:

TRVM, bit [30]:

HCD, bit [29] when EL3 is not implemented:

Otherwise:

TDZ, bit [28]:

TGE, bit [27]:

TVM, bit [26]:

TTLB, bit [25]:

TPU, bit [24]:

TPCP, bit [23]:

TSW, bit [22]:

TACR, bit [21]:

TIDCP, bit [20]:

TSC, bit [19]:

TID3, bit [18]:

TID2, bit [17]:

TID1, bit [16]:

TID0, bit [15] when FEAT_AA32 is implemented:

Otherwise:

TWE, bit [14]:

TWI, bit [13]: