HACR_EL2 | Jon's Arm Reference

Controls trapping to EL2 of IMPLEMENTATION DEFINED aspects of EL1 or EL0 operation.

Arm recommends that the values in this register do not cause unnecessary traps to EL2 when the Effective value of HCR_EL2.{E2H, TGE} == {1, 1}.

Configuration

AArch64 System register HACR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HACR[31:0].

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to HACR_EL2 are UNDEFINED.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

Field descriptions

IMPLEMENTATION DEFINED, bits [63:0]:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HACR_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0001, op2 = 0b111)

if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = HACR_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HACR_EL2;

MSR HACR_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0001, op2 = 0b111)

if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then HACR_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HACR_EL2 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED