Hardware Accelerator for Cleaning Dirty State Consumer Register
Read index for HACDBS structure.
This register is present only when FEAT_HACDBS is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to HACDBSCONS_EL2 are UNDEFINED.
HACDBSCONS_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ERR_REASON | RES0 | ||||||||||||||||||||||||||||||
| RES0 | INDEX | ||||||||||||||||||||||||||||||
Reason for HACDBS error.
| ERR_REASON | Meaning |
|---|---|
| 0b00 |
The PE has not experienced an error while processing the HACDBS. |
| 0b01 |
STRUCTF - A read of an entry from the HACDBS has experienced a fault. |
| 0b10 |
IPAF - A stage 2 walk of an IPA from a HACDBS entry has experienced an MMU fault. |
| 0b11 |
IPAHACF - An entry from the HACDBS experienced an error that is not an MMU fault. |
The reset behavior of this field is:
Reserved, RES0.
This field indicates the index of the HACDBS entry that will be read from next.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, HACDBSCONS_EL2
(op0 = 0b11, op1 = 0b100, CRn = 0b0010, CRm = 0b0011, op2 = 0b101)
if !(IsFeatureImplemented(FEAT_HACDBS) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().HACDBSEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x308); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().HACDBSEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HACDBSCONS_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HACDBSCONS_EL2(); end;
MSR HACDBSCONS_EL2, <Xt>
(op0 = 0b11, op1 = 0b100, CRn = 0b0010, CRm = 0b0011, op2 = 0b101)
if !(IsFeatureImplemented(FEAT_HACDBS) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().HACDBSEn == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x308) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().HACDBSEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HACDBSCONS_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HACDBSCONS_EL2() = X{64}(t); end;
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