Guarded Control Stack Control Register (EL0)
Controls the Guarded Control Stack at EL0.
This register is present only when FEAT_GCS is implemented. Otherwise, direct accesses to GCSCRE0_EL1 are UNDEFINED.
GCSCRE0_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | nTR | STREn | PUSHMEn | RES0 | RVCHKEN | RES0 | PCRSEL | ||||||||||||||||||||||||
Reserved, RES0.
Trap GCS register accesses from EL0.
| nTR | Meaning |
|---|---|
| 0b0 |
Read accesses to GCSPR_EL0 at EL0 cause a Trap exception. |
| 0b1 |
This control does not cause any instructions to be trapped. |
The reset behavior of this field is:
Execution of the following instructions are trapped:
| STREn | Meaning |
|---|---|
| 0b0 |
Execution of any of the specified instructions at EL0 cause a GCS exception. |
| 0b1 |
This control does not cause any instructions to be trapped. |
The reset behavior of this field is:
Trap GCSPUSHM instruction.
| PUSHMEn | Meaning |
|---|---|
| 0b0 |
Execution of a GCSPUSHM instruction at EL0 causes a Trap exception. |
| 0b1 |
This control does not cause any instructions to be trapped. |
The reset behavior of this field is:
Reserved, RES0.
Return value check enable.
| RVCHKEN | Meaning |
|---|---|
| 0b0 |
Return value checking disabled at EL0. |
| 0b1 |
Return value checking enabled at EL0. |
The reset behavior of this field is:
Reserved, RES0.
Guarded Control Stack procedure call return enable selection.
| PCRSEL | Meaning |
|---|---|
| 0b0 |
Guarded Control Stack at EL0 is not PCR Selected. |
| 0b1 |
Guarded Control Stack at EL0 is PCR Selected. |
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, GCSCRE0_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b0010, CRm = 0b0101, op2 = 0b010)
if !IsFeatureImplemented(FEAT_GCS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.GCSEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.nGCS_EL0 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.GCSEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = GCSCRE0_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.GCSEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.GCSEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = GCSCRE0_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = GCSCRE0_EL1;
MSR GCSCRE0_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b0010, CRm = 0b0101, op2 = 0b010)
if !IsFeatureImplemented(FEAT_GCS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.GCSEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.nGCS_EL0 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.GCSEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else GCSCRE0_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.GCSEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.GCSEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else GCSCRE0_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then GCSCRE0_EL1 = X[t, 64];
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