Exception Link Register (EL1)
When taking an exception to EL1, holds the address to return to.
This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to ELR_EL1 are UNDEFINED.
This register is a Special-purpose register.
ELR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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Return address.
An exception return from EL1 using AArch64 makes ELR_EL1 become UNKNOWN.
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name ELR_EL1 or ELR_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ELR_EL1
(op0 = 0b11, op1 = 0b000, CRn = 0b0100, CRm = 0b0000, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '011' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x230); else X{64}(t) = ELR_EL1(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X{64}(t) = ELR_EL2(); else X{64}(t) = ELR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ELR_EL1(); end;
MSR ELR_EL1, <Xt>
(op0 = 0b11, op1 = 0b000, CRn = 0b0100, CRm = 0b0000, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && !(EffectiveHCR_EL2_NVx() IN {'x11'}) then EXLOCKException(); elsif EffectiveHCR_EL2_NVx() == '011' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x230) = X{64}(t); else ELR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && ELIsInHost(EL2) then EXLOCKException(); elsif ELIsInHost(EL2) then ELR_EL2() = X{64}(t); else ELR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then ELR_EL1() = X{64}(t); end;
MRS <Xt>, ELR_EL12
(op0 = 0b11, op1 = 0b101, CRn = 0b0100, CRm = 0b0000, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x230); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X{64}(t) = ELR_EL1(); else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = ELR_EL1(); else Undefined(); end; end;
MSR ELR_EL12, <Xt>
(op0 = 0b11, op1 = 0b101, CRn = 0b0100, CRm = 0b0000, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x230) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then ELR_EL1() = X{64}(t); else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then ELR_EL1() = X{64}(t); else Undefined(); end; end;
MRS <Xt>, ELR_EL2
(op0 = 0b11, op1 = 0b100, CRn = 0b0100, CRm = 0b0000, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = ELR_EL1(); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = ELR_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = ELR_EL2(); end;
MSR ELR_EL2, <Xt>
(op0 = 0b11, op1 = 0b100, CRn = 0b0100, CRm = 0b0000, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && EffectiveHCR_EL2_NVx() IN {'xx1'} then EXLOCKException(); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then ELR_EL1() = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' then EXLOCKException(); else ELR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then ELR_EL2() = X{64}(t); end;
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