DC GBVA

Executing DC GBVA

When this instruction is executed, it can generate memory faults or watchpoints which are prioritized in the same way as other memory-related faults or watchpoints. If a synchronous Data Abort fault or a watchpoint is generated, the CM bit in the ESR_ELx.ISS field is not set.

For a DC GBVA instruction executed to any type of Device memory, it is CONSTRAINED UNPREDICTABLE whether it generates an Alignment Fault determined by the memory type. Allocation tags at the specified addresses are not modified.

This instruction applies to Normal memory regardless of cacheability attributes.

This instruction behaves as a set of stores to each Allocation Tag within the block being accessed, and so it:

• Generates a Permission fault if the translation system does not permit writes to the locations.
• Requires the same considerations for ordering and the management of coherency as any other store instructions.

This system instruction is an alias of the SYS instruction.

Accesses to this instruction use the following encodings in the System instruction encoding space:

(op0 = 0b01, op1 = 0b011, CRn = 0b0111, CRm = 0b0100, op2 = 0b111)

if !IsFeatureImplemented(FEAT_MTETC) then Undefined(); elsif PSTATE.EL == EL0 then if EffectivelyAtEL0NotInHost() && SCTLR_EL1().DZE == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && HCR_EL2().TDZ == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT2) && (!HaveEL(EL3) || SCR_EL3().FGTEn2 == '1') && HFGITR2_EL2().DCGBVA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectivelyAtEL0InHost() && SCTLR_EL2().DZE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_MemZero(X{64}(t), CacheType_TagWrite); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TDZ == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && (!HaveEL(EL3) || SCR_EL3().FGTEn2 == '1') && HFGITR2_EL2().DCGBVA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_MemZero(X{64}(t), CacheType_TagWrite); end; elsif PSTATE.EL == EL2 then AArch64_MemZero(X{64}(t), CacheType_TagWrite); elsif PSTATE.EL == EL3 then AArch64_MemZero(X{64}(t), CacheType_TagWrite); end;