Debug Data Transfer Register, half-duplex
Transfers 64 bits of data between the PE and an external debugger. Can transfer both ways using only a single register.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to AArch32 System register DBGDTRRXint[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to External register DBGDTRRX_EL0[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to AArch64 System register DBGDTRRX_EL0[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRTXint[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to External register DBGDTRTX_EL0[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to AArch64 System register DBGDTRTX_EL0[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to AArch32 System register DBGDTRTXint[31:0] when read.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to External register DBGDTRTX_EL0[31:0] when read.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to AArch64 System register DBGDTRTX_EL0[31:0] when read.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRRXint[31:0] when read.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to External register DBGDTRRX_EL0[31:0] when read.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to AArch64 System register DBGDTRRX_EL0[31:0] when read.
This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to DBGDTR_EL0 are UNDEFINED.
DBGDTR_EL0 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HighWord | |||||||||||||||||||||||||||||||
| LowWord | |||||||||||||||||||||||||||||||
If TXfull is 1, then writes to this register set DTRRX to an UNKNOWN value. Otherwise, writes to this register set DTRRX to the value in this field. Writes to this register do not change RXfull.
Reads of this register:
If RXfull is 1, return the last value written to DTRTX.
If RXfull is 0, return an UNKNOWN value.
After the read, RXfull is cleared to 0.
If TXfull is 1, then writes to this register set DTRTX to an UNKNOWN value. Otherwise, writes to this register set DTRTX to the value in this field and set TXfull to 1.
Reads of this register:
If RXfull is 1, return the last value written to DTRRX.
If RXfull is 0, return an UNKNOWN value.
After the read, RXfull is cleared to 0.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, DBGDTR_EL0
(op0 = 0b10, op1 = 0b011, CRn = 0b0000, CRm = 0b0100, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif Halted() then X{64}(t) = Read_DBGDTR_EL0{64}(); elsif PSTATE.EL == EL0 then if MDSCR_EL1().TDCC == '1' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (EffectiveTGEforEL0Traps() == '1' || MDCR_EL2().[TDE,TDA] != '00') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = Read_DBGDTR_EL0{64}(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = Read_DBGDTR_EL0{64}(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = Read_DBGDTR_EL0{64}(); end; elsif PSTATE.EL == EL3 then X{64}(t) = Read_DBGDTR_EL0{64}(); end;
MSR DBGDTR_EL0, <Xt>
(op0 = 0b10, op1 = 0b011, CRn = 0b0000, CRm = 0b0100, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif Halted() then Write_DBGDTR_EL0{64}(X{64}(t)); elsif PSTATE.EL == EL0 then if MDSCR_EL1().TDCC == '1' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (EffectiveTGEforEL0Traps() == '1' || MDCR_EL2().[TDE,TDA] != '00') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else Write_DBGDTR_EL0{64}(X{64}(t)); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else Write_DBGDTR_EL0{64}(X{64}(t)); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else Write_DBGDTR_EL0{64}(X{64}(t)); end; elsif PSTATE.EL == EL3 then Write_DBGDTR_EL0{64}(X{64}(t)); end;
Version 2026.06 — Copyright © 2010-2026 Arm Limited or its affiliates.
This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.