DAIF

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to DAIF are UNDEFINED.

Attributes

Field descriptions

Bits [63:10]:

D, bit [9]:

Process state D mask.

D	Meaning
0b0	Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are not masked.
0b1	Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are masked.

When the target Exception level of the debug exception is higher than the current Exception level, the exception is not masked by this bit.

The reset behavior of this field is:

On a Warm reset, this field resets to '1'.

A, bit [8]:

I, bit [7]:

F, bit [6]:

Bits [5:0]:

A	Meaning
0b0	Exception not masked.
0b1	Exception masked.

I	Meaning
0b0	Exception not masked.
0b1	Exception masked.

F	Meaning
0b0	Exception not masked.
0b1	Exception masked.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, DAIF

(op0 = 0b11, op1 = 0b011, CRn = 0b0100, CRm = 0b0010, op2 = 0b001)

if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif PSTATE.EL == EL0 then if ELIsInHost(EL0) || SCTLR_EL1.UMA == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else X[t, 64] = Zeros(54):PSTATE.<D,A,I,F>:Zeros(6); elsif PSTATE.EL == EL1 then X[t, 64] = Zeros(54):PSTATE.<D,A,I,F>:Zeros(6); elsif PSTATE.EL == EL2 then X[t, 64] = Zeros(54):PSTATE.<D,A,I,F>:Zeros(6); elsif PSTATE.EL == EL3 then X[t, 64] = Zeros(54):PSTATE.<D,A,I,F>:Zeros(6);

MSR DAIF, <Xt>

(op0 = 0b11, op1 = 0b011, CRn = 0b0100, CRm = 0b0010, op2 = 0b001)

if !IsFeatureImplemented(FEAT_AA64) then UNDEFINED; elsif PSTATE.EL == EL0 then if ELIsInHost(EL0) || SCTLR_EL1.UMA == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else PSTATE.<D,A,I,F> = X[t, 64]<9:6>; elsif PSTATE.EL == EL1 then PSTATE.<D,A,I,F> = X[t, 64]<9:6>; elsif PSTATE.EL == EL2 then PSTATE.<D,A,I,F> = X[t, 64]<9:6>; elsif PSTATE.EL == EL3 then PSTATE.<D,A,I,F> = X[t, 64]<9:6>;

MSR DAIFSet, #<imm>

(op0 = 0b00, op1 = 0b011, CRn = 0b0100, op2 = 0b110)

MSR DAIFClr, #<imm>

(op0 = 0b00, op1 = 0b011, CRn = 0b0100, op2 = 0b111)

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																						D	A	I	F	RES0

Configuration