Cache Size Selection Register
Selects the current Cache Size ID Register, CCSIDR_EL1, by specifying the required cache level and the cache type (either instruction or data cache).
AArch64 System register CSSELR_EL1 bits [31:0] are architecturally mapped to AArch32 System register CSSELR[31:0].
This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to CSSELR_EL1 are UNDEFINED.
CSSELR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | TnD | Level | InD | ||||||||||||||||||||||||||||
Reserved, RES0.
Allocation Tag not Data bit.
| TnD | Meaning |
|---|---|
| 0b0 |
Data, Instruction or Unified cache. |
| 0b1 |
Separate Allocation Tag cache. |
When CSSELR_EL1.InD == 1, this bit is RES0.
If CSSELR_EL1.{TnD, Level, InD} is programmed to a cache level that is not implemented, then the value for this field on a read of CSSELR_EL1 is UNKNOWN.
The reset behavior of this field is:
Reserved, RES0.
Cache level of required cache.
| Level | Meaning |
|---|---|
| 0b000 |
Level 1 cache. |
| 0b001 |
Level 2 cache. |
| 0b010 |
Level 3 cache. |
| 0b011 |
Level 4 cache. |
| 0b100 |
Level 5 cache. |
| 0b101 |
Level 6 cache. |
| 0b110 |
Level 7 cache. |
All other values are reserved.
If CSSELR_EL1.{TnD, Level, InD} is programmed to a cache level that is not implemented, then the value for this field on a read of CSSELR_EL1 is UNKNOWN.
The reset behavior of this field is:
Instruction not Data bit.
| InD | Meaning |
|---|---|
| 0b0 |
Data or unified cache. |
| 0b1 |
Instruction cache. |
If CSSELR_EL1.{TnD, Level, InD} is programmed to a cache level that is not implemented, then a read of CSSELR_EL1 is CONSTRAINED UNPREDICTABLE, and returns UNKNOWN values for CSSELR_EL1.{Level, InD}.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, CSSELR_EL1
(op0 = 0b11, op1 = 0b010, CRn = 0b0000, CRm = 0b0000, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TID2 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_EVT) && HCR_EL2().TID4 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().CSSELR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = CSSELR_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = CSSELR_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = CSSELR_EL1(); end;
MSR CSSELR_EL1, <Xt>
(op0 = 0b11, op1 = 0b010, CRn = 0b0000, CRm = 0b0000, op2 = 0b000)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TID2 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_EVT) && HCR_EL2().TID4 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().CSSELR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else CSSELR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then CSSELR_EL1() = X{64}(t); elsif PSTATE.EL == EL3 then CSSELR_EL1() = X{64}(t); end;
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