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CPTRMASK_EL2

Architectural Feature Trap Masking Register

Mask register to prevent updates of fields in CPTR_EL2 on writes.

Configuration

This register is present only when FEAT_SRMASK is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to CPTRMASK_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

CPTRMASK_EL2 is a 64-bit register.

Field descriptions

When ELIsInHost(EL2):

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
TCPACTAME0POETTARES0SMENRES0FPENRES0ZENRES0

Bits [63:32]:

Reserved, RES0.

TCPAC, bit [31]:

Mask bit for TCPAC.

TCPACMeaning
0b0

CPTR_EL2.TCPAC is writeable.

0b1

CPTR_EL2.TCPAC is not writeable.

The reset behavior of this field is:

TAM, bit [30] when FEAT_AMUv1 is implemented:

Mask bit for TAM.

TAMMeaning
0b0

CPTR_EL2.TAM is writeable.

0b1

CPTR_EL2.TAM is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

E0POE, bit [29] when FEAT_S1POE is implemented:

Mask bit for E0POE.

E0POEMeaning
0b0

CPTR_EL2.E0POE is writeable.

0b1

CPTR_EL2.E0POE is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

TTA, bit [28] when System register access to the trace unit registers is implemented:

Mask bit for TTA.

TTAMeaning
0b0

CPTR_EL2.TTA is writeable.

0b1

CPTR_EL2.TTA is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [27:25]:

Reserved, RES0.

SMEN, bit [24] when FEAT_SME is implemented:

Mask bit for SMEN.

SMENMeaning
0b0

CPTR_EL2.SMEN is writeable.

0b1

CPTR_EL2.SMEN is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [23:21]:

Reserved, RES0.

FPEN, bit [20]:

Mask bit for FPEN.

FPENMeaning
0b0

CPTR_EL2.FPEN is writeable.

0b1

CPTR_EL2.FPEN is not writeable.

The reset behavior of this field is:

Bits [19:17]:

Reserved, RES0.

ZEN, bit [16] when FEAT_SVE is implemented:

Mask bit for ZEN.

ZENMeaning
0b0

CPTR_EL2.ZEN is writeable.

0b1

CPTR_EL2.ZEN is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [15:0]:

Reserved, RES0.

Otherwise:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
TCPACTAMRES0TTARES0TSMRES0TFPRES0TZRES0

This format applies in all Armv8.0 implementations.

Bits [63:32]:

Reserved, RES0.

TCPAC, bit [31]:

Mask bit for TCPAC.

TCPACMeaning
0b0

CPTR_EL2.TCPAC is writeable.

0b1

CPTR_EL2.TCPAC is not writeable.

The reset behavior of this field is:

TAM, bit [30] when FEAT_AMUv1 is implemented:

Mask bit for TAM.

TAMMeaning
0b0

CPTR_EL2.TAM is writeable.

0b1

CPTR_EL2.TAM is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [29:21]:

Reserved, RES0.

TTA, bit [20]:

Mask bit for TTA.

TTAMeaning
0b0

CPTR_EL2.TTA is writeable.

0b1

CPTR_EL2.TTA is not writeable.

The reset behavior of this field is:

Bits [19:13]:

Reserved, RES0.

TSM, bit [12] when FEAT_SME is implemented:

Mask bit for TSM.

TSMMeaning
0b0

CPTR_EL2.TSM is writeable.

0b1

CPTR_EL2.TSM is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bit [11]:

Reserved, RES0.

TFP, bit [10]:

Mask bit for TFP.

TFPMeaning
0b0

CPTR_EL2.TFP is writeable.

0b1

CPTR_EL2.TFP is not writeable.

The reset behavior of this field is:

Bit [9]:

Reserved, RES0.

TZ, bit [8] when FEAT_SVE is implemented:

Mask bit for TZ.

TZMeaning
0b0

CPTR_EL2.TZ is writeable.

0b1

CPTR_EL2.TZ is not writeable.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [7:0]:

Reserved, RES0.

Access Instructions

When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name CPTRMASK_EL2 or CPTRMASK_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, CPTRMASK_EL2

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = CPTRMASK_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = CPTRMASK_EL2;

MSR CPTRMASK_EL2, <Xt>

(op0 = 0b11, op1 = 0b100, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !IsZero(EffectiveCPTRMASK_EL2()) then UNDEFINED; else CPTRMASK_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then CPTRMASK_EL2 = X[t, 64];

MRS <Xt>, CPACRMASK_EL1

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGRTR2_EL2.nCPACRMASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x320]; else X[t, 64] = CPACRMASK_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = CPTRMASK_EL2; else X[t, 64] = CPACRMASK_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = CPACRMASK_EL1;

MSR CPACRMASK_EL1, <Xt>

(op0 = 0b11, op1 = 0b000, CRn = 0b0001, CRm = 0b0100, op2 = 0b010)

if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HFGWTR2_EL2.nCPACRMASK_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SRMASKEn == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem[0x320] = X[t, 64]; elsif !IsZero(EffectiveCPACRMASK_EL1()) then UNDEFINED; else CPACRMASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SRMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SRMASKEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then if !IsZero(EffectiveCPTRMASK_EL2()) then UNDEFINED; else CPTRMASK_EL2 = X[t, 64]; else CPACRMASK_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then CPACRMASK_EL1 = X[t, 64];

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