Counter-timer Secure Virtual Timer Control Register (EL2)
Control register for the Secure EL2 virtual timer.
AArch64 System register CNTHVS_CTL_EL2 bits [31:0] are architecturally mapped to AArch32 System register CNTHVS_CTL[31:0].
This register is present only when FEAT_SEL2 is implemented, FEAT_VHE is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to CNTHVS_CTL_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
CNTHVS_CTL_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | ISTATUS | IMASK | ENABLE | ||||||||||||||||||||||||||||
Reserved, RES0.
The status of the timer. This bit indicates whether the timer condition is met:
| ISTATUS | Meaning |
|---|---|
| 0b0 |
Timer condition is not met. |
| 0b1 |
Timer condition is met. |
When the value of the CNTHVS_CTL_EL2.ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.
When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
The reset behavior of this field is:
Access to this field is RO.
Timer interrupt mask bit. Permitted values are:
| IMASK | Meaning |
|---|---|
| 0b0 |
Timer interrupt is not masked by the IMASK bit. |
| 0b1 |
Timer interrupt is masked by the IMASK bit. |
For more information, see the description of the CNTHVS_CTL_EL2.ISTATUS bit.
The reset behavior of this field is:
Enables the timer. Permitted values are:
| ENABLE | Meaning |
|---|---|
| 0b0 |
Timer disabled. |
| 0b1 |
Timer enabled. |
Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTHVS_TVAL_EL2 continues to count down.
Disabling the output signal might be a power-saving option.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, CNTHVS_CTL_EL2
(op0 = 0b11, op1 = 0b100, CRn = 0b1110, CRm = 0b0100, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_SEL2) && IsFeatureImplemented(FEAT_VHE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if !IsCurrentSecurityState(SS_Secure) then Undefined(); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if !IsCurrentSecurityState(SS_Secure) then Undefined(); else X{64}(t) = CNTHVS_CTL_EL2(); end; elsif PSTATE.EL == EL3 then if SCR_EL3().EEL2 == '0' then Undefined(); else X{64}(t) = CNTHVS_CTL_EL2(); end; end;
MSR CNTHVS_CTL_EL2, <Xt>
(op0 = 0b11, op1 = 0b100, CRn = 0b1110, CRm = 0b0100, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_SEL2) && IsFeatureImplemented(FEAT_VHE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if !IsCurrentSecurityState(SS_Secure) then Undefined(); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if !IsCurrentSecurityState(SS_Secure) then Undefined(); else CNTHVS_CTL_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then if SCR_EL3().EEL2 == '0' then Undefined(); else CNTHVS_CTL_EL2() = X{64}(t); end; end;
MRS <Xt>, CNTV_CTL_EL0
(op0 = 0b11, op1 = 0b011, CRn = 0b1110, CRm = 0b0011, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif EffectivelyAtEL0NotInHost() then if CNTKCTL_EL1().EL0VTEN == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_ECV) && CNTHCTL_EL2().EL1TVT == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = CNTV_CTL_EL0(); end; elsif EffectivelyAtEL0InHost() then if CNTHCTL_EL2().EL0VTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif IsCurrentSecurityState(SS_Secure) then X{64}(t) = CNTHVS_CTL_EL2(); else X{64}(t) = CNTHV_CTL_EL2(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_ECV) && CNTHCTL_EL2().EL1TVT == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x170); else X{64}(t) = CNTV_CTL_EL0(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then X{64}(t) = CNTHVS_CTL_EL2(); elsif ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure) then X{64}(t) = CNTHV_CTL_EL2(); else X{64}(t) = CNTV_CTL_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = CNTV_CTL_EL0(); end;
MSR CNTV_CTL_EL0, <Xt>
(op0 = 0b11, op1 = 0b011, CRn = 0b1110, CRm = 0b0011, op2 = 0b001)
if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif EffectivelyAtEL0NotInHost() then if CNTKCTL_EL1().EL0VTEN == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_ECV) && CNTHCTL_EL2().EL1TVT == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else CNTV_CTL_EL0() = X{64}(t); end; elsif EffectivelyAtEL0InHost() then if CNTHCTL_EL2().EL0VTEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif IsCurrentSecurityState(SS_Secure) then CNTHVS_CTL_EL2() = X{64}(t); else CNTHV_CTL_EL2() = X{64}(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_ECV) && CNTHCTL_EL2().EL1TVT == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x170) = X{64}(t); else CNTV_CTL_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHVS_CTL_EL2() = X{64}(t); elsif ELIsInHost(EL2) && !IsCurrentSecurityState(SS_Secure) then CNTHV_CTL_EL2() = X{64}(t); else CNTV_CTL_EL0() = X{64}(t); end; elsif PSTATE.EL == EL3 then CNTV_CTL_EL0() = X{64}(t); end;
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