Branch Record Buffer Control Register (EL2)
Controls the Branch Record Buffer.
This register is present only when FEAT_BRBE is implemented. Otherwise, direct accesses to BRBCR_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
BRBCR_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | EXCEPTION | ERTN | RES0 | FZPSS | FZP | RES0 | TS | MPRED | CC | RES0 | E2BRE | E0HBRE | |||||||||||||||||||
Reserved, RES0.
Enable the recording of entry to EL2 through an exception.
| EXCEPTION | Meaning |
|---|---|
| 0b0 |
Disable the recording of Branch records for exceptions when taken to EL2. |
| 0b1 |
Enable the recording of Branch records for exceptions when taken to EL2. |
The reset behavior of this field is:
Allow the recording Branch records for exception return instructions from EL2.
| ERTN | Meaning |
|---|---|
| 0b0 |
Disable the recording Branch records for exception return instructions from EL2. |
| 0b1 |
Enable the recording Branch records for exception return instructions from EL2. |
The reset behavior of this field is:
Reserved, RES0.
Freeze BRBE on PMU Snapshot.
| FZPSS | Meaning |
|---|---|
| 0b0 |
Branch recording is not affected by this control. |
| 0b1 |
If BRBCR_EL1.FZPSS is 1, then a BRBE freeze event occurs when a PMU snapshot occurs. |
The reset behavior of this field is:
Reserved, RES0.
Freeze BRBE on PMU overflow.
| FZP | Meaning |
|---|---|
| 0b0 |
Branch recording is not affected by this control. |
| 0b1 | A BRBE freeze event occurs when the PE is in a Non-prohibited region, BRBFCR_EL1.PAUSED is 0, and, for any event counter PMEVCNTR<m>_EL0 in the second range, PMOVSCLR_EL0[m] is 1. For more information about event counter ranges, see MDCR_EL2.HPMN. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Timestamp Control.
| TS | Meaning | Applies when |
|---|---|---|
| 0b00 |
Timestamp controlled by BRBCR_EL1.TS. | |
| 0b01 |
Virtual timestamp. The BRBE recorded timestamp is the physical counter value, minus the value of CNTVOFF_EL2. | |
| 0b10 | Guest physical timestamp. The BRBE recorded timestamp is the physical counter value minus a physical offset. If any of the following are true, the physical offset is zero, otherwise the physical offset is the value of CNTPOFF_EL2:
| When FEAT_ECV is implemented |
| 0b11 |
Physical timestamp. The BRBE recorded timestamp is the physical counter value. |
The reset behavior of this field is:
Mask the recording of mispredicts.
| MPRED | Meaning |
|---|---|
| 0b0 |
Disable the recording of mispredict information. |
| 0b1 |
Allow the recording of mispredict information. |
If EL2 is not implemented, then the Effective value of this field is 1, other than for a direct read of the register.
The reset behavior of this field is:
Enable the recording of cycle count information.
| CC | Meaning |
|---|---|
| 0b0 |
Disable the recording of cycle count information. |
| 0b1 |
Allow the recording of cycle count information. |
If EL2 is not implemented, then the Effective value of this field is 1, other than for a direct read of the register.
The reset behavior of this field is:
Reserved, RES0.
EL2 Branch recording enable.
| E2BRE | Meaning |
|---|---|
| 0b0 |
Branch recording prohibited at EL2. |
| 0b1 |
Branch recording enabled at EL2. |
The reset behavior of this field is:
EL0 Branch recording enable.
| E0HBRE | Meaning |
|---|---|
| 0b0 |
Branch recording prohibited at EL0 when the Effective value of HCR_EL2.TGE is 1. |
| 0b1 |
Branch recording enabled at EL0 when the Effective value of HCR_EL2.TGE is 1. |
This field is ignored by the PE when any of the following are true:
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name BRBCR_EL2 or BRBCR_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, BRBCR_EL1
(op0 = 0b10, op1 = 0b001, CRn = 0b1001, CRm = 0b0000, op2 = 0b000)
if !IsFeatureImplemented(FEAT_BRBE) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().nBRBCTL == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x8E0); else X{64}(t) = BRBCR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = BRBCR_EL2(); else X{64}(t) = BRBCR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = BRBCR_EL1(); end;
MRS <Xt>, BRBCR_EL2
(op0 = 0b10, op1 = 0b100, CRn = 0b1001, CRm = 0b0000, op2 = 0b000)
if !IsFeatureImplemented(FEAT_BRBE) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = BRBCR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = BRBCR_EL2(); end;
MSR BRBCR_EL1, <Xt>
(op0 = 0b10, op1 = 0b001, CRn = 0b1001, CRm = 0b0000, op2 = 0b000)
if !IsFeatureImplemented(FEAT_BRBE) then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && !(EffectivelyAtEL0InHost() || EffectivelyAtEL0NotInHost() || PSTATE.EL == EL3) && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().nBRBCTL == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x8E0) = X{64}(t); else BRBCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then BRBCR_EL2() = X{64}(t); else BRBCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then BRBCR_EL1() = X{64}(t); end;
MSR BRBCR_EL2, <Xt>
(op0 = 0b10, op1 = 0b100, CRn = 0b1001, CRm = 0b0000, op2 = 0b000)
if !IsFeatureImplemented(FEAT_BRBE) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3().SBRBE != '11' && SCR_EL3().NS == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().SBRBE IN {'x0'} && SCR_EL3().NS == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else BRBCR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then BRBCR_EL2() = X{64}(t); end;
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