Activity Monitors Event Type Registers 0
Provides information on the events that an architected activity monitor event counter AMEVCNTR0<n>_EL0 counts.
AArch64 System register AMEVTYPER0<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register AMEVTYPER0<n>[31:0].
AArch64 System register AMEVTYPER0<n>_EL0 bits [31:0] are architecturally mapped to External register AMEVTYPER0<n>[31:0].
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMEVTYPER0<n>_EL0 are UNDEFINED.
AMEVTYPER0<n>_EL0 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | evtCount | ||||||||||||||||||||||||||||||
Reserved, RES0.
Event to count. The event number of the event that is counted by the architected activity monitor event counter AMEVCNTR0<n>_EL0. The value of this field is architecturally mandated for each architected counter.
The following table shows the mapping between required event numbers and the corresponding counters:
| evtCount | Meaning | Applies when |
|---|---|---|
| 0x0011 |
Processor frequency cycles. | When n == 0 |
| 0x4004 |
Constant frequency cycles. | When n == 1 |
| 0x0008 |
Instructions retired. | When n == 2 |
| 0x4005 |
Memory stall cycles. | When n == 3 |
Access to this field is RO.
If <n> is greater than or equal to the number of architected activity monitor event counters, reads and writes of AMEVTYPER0<n>_EL0 are UNDEFINED.
AMCGCR_EL0.CG0NC identifies the number of architected activity monitor event counters.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, AMEVTYPER0<m>_EL0 ; Where m = 0-3
(op0 = 0b11, op1 = 0b011, CRn = 0b1101, CRm = 0b011:m[3], op2 = m[2:0])
let m:integer = UInt(CRm[0] :: op2[2:0]); if !IsFeatureImplemented(FEAT_AMUv1) then Undefined(); elsif m >= 4 then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif PSTATE.EL == EL0 then if AMUSERENR_EL0().EN == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMEVTYPER0_EL0(m); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMEVTYPER0_EL0(m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMEVTYPER0_EL0(m); end; elsif PSTATE.EL == EL3 then X{64}(t) = AMEVTYPER0_EL0(m); end;
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