Activity Monitors Event Counter Virtual Offset Registers 0
Holds the 64-bit virtual offset for architected activity monitor events.
This register is present only when FEAT_AMUv1p1 is implemented. Otherwise, direct accesses to AMEVCNTVOFF0<n>_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
AMEVCNTVOFF0<n>_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VOffset | |||||||||||||||||||||||||||||||
| VOffset | |||||||||||||||||||||||||||||||
Virtual offset.
The reset behavior of this field is:
If <n> is not 0, 2 or 3, reads and writes of AMEVCNTVOFF0<n>_EL2 are UNDEFINED.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, AMEVCNTVOFF0<m>_EL2 ; Where m = 0-15
(op0 = 0b11, op1 = 0b100, CRn = 0b1101, CRm = 0b100:m[3], op2 = m[2:0])
let m:integer = UInt(CRm[0] :: op2[2:0]); if !IsFeatureImplemented(FEAT_AMUv1p1) then Undefined(); elsif m >= 4 then Undefined(); elsif !(m IN {0, 2, 3}) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().AMVOFFEN == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0xA00 + (8 * m)); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().AMVOFFEN == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMEVCNTVOFF0_EL2(m); end; elsif PSTATE.EL == EL3 then X{64}(t) = AMEVCNTVOFF0_EL2(m); end;
MSR AMEVCNTVOFF0<m>_EL2, <Xt> ; Where m = 0-15
(op0 = 0b11, op1 = 0b100, CRn = 0b1101, CRm = 0b100:m[3], op2 = m[2:0])
let m:integer = UInt(CRm[0] :: op2[2:0]); if !IsFeatureImplemented(FEAT_AMUv1p1) then Undefined(); elsif m >= 4 then Undefined(); elsif !(m IN {0, 2, 3}) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL == EL2 && EL3SDDUndefPriority() && SCR_EL3().AMVOFFEN == '0' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0xA00 + (8 * m)) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && SCR_EL3().AMVOFFEN == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AMEVCNTVOFF0_EL2(m) = X{64}(t); end; elsif PSTATE.EL == EL3 then AMEVCNTVOFF0_EL2(m) = X{64}(t); end;
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