Activity Monitors Count Enable Set Register 0
Enable control bits for the architected activity monitors event counters, AMEVCNTR0<n>_EL0.
AArch64 System register AMCNTENSET0_EL0 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENSET0[31:0].
AArch64 System register AMCNTENSET0_EL0 bits [31:0] are architecturally mapped to External register AMCNTENSET0[31:0].
AArch64 System register AMCNTENSET0_EL0 bits [31:0] are architecturally mapped to External register AMCNTENSET[31:0].
AArch64 System register AMCNTENSET0_EL0 bits [31:0] are architecturally mapped to External register AMCNTENCLR0[31:0].
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCNTENSET0_EL0 are UNDEFINED.
AMCNTENSET0_EL0 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | RAZ/WI | P3 | P2 | P1 | P0 | ||||||||||||||||||||||||||
Reserved, RES0.
Reserved, RAZ/WI.
This field is reserved for additional architected activity monitor event counters, which Arm might define in a future version of the Activity Monitors architecture.
Activity monitor event counter enable bit for AMEVCNTR0<n>_EL0.
AMCGCR_EL0.CG0NC identifies the number of architected activity monitor event counters. In an implementation that includes FEAT_AMUv1, the number of architected activity monitor event counters is 4.
Possible values of each bit are:
| P<n> | Meaning |
|---|---|
| 0b0 |
When read, means that AMEVCNTR0<n>_EL0 is disabled. When written, has no effect. |
| 0b1 |
When read, means that AMEVCNTR0<n>_EL0 is enabled. When written, enables AMEVCNTR0<n>_EL0. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, AMCNTENSET0_EL0
(op0 = 0b11, op1 = 0b011, CRn = 0b1101, CRm = 0b0010, op2 = 0b101)
if !IsFeatureImplemented(FEAT_AMUv1) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif PSTATE.EL == EL0 then if AMUSERENR_EL0().EN == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HAFGRTR_EL2().AMCNTEN0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCNTENSET0_EL0(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HAFGRTR_EL2().AMCNTEN0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCNTENSET0_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCNTENSET0_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = AMCNTENSET0_EL0(); end;
MSR AMCNTENSET0_EL0, <Xt>
(op0 = 0b11, op1 = 0b011, CRn = 0b1101, CRm = 0b0010, op2 = 0b101)
if !IsFeatureImplemented(FEAT_AMUv1) then Undefined(); elsif IsHighestEL(PSTATE.EL) then AMCNTENSET0_EL0() = X{64}(t); else Undefined(); end;
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